{"id":2215437,"url":"http://patchwork.ozlabs.org/api/patches/2215437/?format=json","web_url":"http://patchwork.ozlabs.org/project/intel-wired-lan/patch/20260324153542.674859-1-aleksandr.loktionov@intel.com/","project":{"id":46,"url":"http://patchwork.ozlabs.org/api/projects/46/?format=json","name":"Intel Wired Ethernet development","link_name":"intel-wired-lan","list_id":"intel-wired-lan.osuosl.org","list_email":"intel-wired-lan@osuosl.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260324153542.674859-1-aleksandr.loktionov@intel.com>","list_archive_url":null,"date":"2026-03-24T15:35:42","name":"[iwl-next,v3] ice: add 200G_AUI8 PHY type definitions and wire them up","commit_ref":null,"pull_url":null,"state":"changes-requested","archived":false,"hash":"495d6cc40541306d36939a8ef178e058d03e2e17","submitter":{"id":75597,"url":"http://patchwork.ozlabs.org/api/people/75597/?format=json","name":"Loktionov, Aleksandr","email":"aleksandr.loktionov@intel.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/intel-wired-lan/patch/20260324153542.674859-1-aleksandr.loktionov@intel.com/mbox/","series":[{"id":497307,"url":"http://patchwork.ozlabs.org/api/series/497307/?format=json","web_url":"http://patchwork.ozlabs.org/project/intel-wired-lan/list/?series=497307","date":"2026-03-24T15:35:42","name":"[iwl-next,v3] ice: add 200G_AUI8 PHY type definitions and wire them up","version":3,"mbox":"http://patchwork.ozlabs.org/series/497307/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2215437/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2215437/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":["incoming@patchwork.ozlabs.org","intel-wired-lan@lists.osuosl.org"],"Delivered-To":["patchwork-incoming@legolas.ozlabs.org","intel-wired-lan@lists.osuosl.org"],"Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=osuosl.org header.i=@osuosl.org header.a=rsa-sha256\n header.s=default header.b=6Yq3hb6d;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=osuosl.org\n (client-ip=2605:bc80:3010::138; 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a=\"85699281\"","E=Sophos;i=\"6.23,138,1770624000\"; d=\"scan'208\";a=\"85699281\"","E=Sophos;i=\"6.23,138,1770624000\"; d=\"scan'208\";a=\"262316423\""],"X-ExtLoop1":"1","From":"Aleksandr Loktionov ","To":"intel-wired-lan@lists.osuosl.org, anthony.l.nguyen@intel.com,\n aleksandr.loktionov@intel.com","Cc":"netdev@vger.kernel.org, Paul Greenwalt ,\n Simon Horman , Paul Menzel ","Date":"Tue, 24 Mar 2026 16:35:42 +0100","Message-ID":"<20260324153542.674859-1-aleksandr.loktionov@intel.com>","X-Mailer":"git-send-email 2.52.0","MIME-Version":"1.0","Content-Transfer-Encoding":"8bit","X-Mailman-Original-DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1774366546; x=1805902546;\n h=from:to:cc:subject:date:message-id:mime-version:\n content-transfer-encoding;\n bh=5pG6qL+qH5cMyGmxtdL+xaxp+WIPMwnR4xxdBctIYnc=;\n b=OrcoPhrWgQJ2+1E3LnZYOzEDonGmU42EbGbUpsq4vqNreKL3dvFRYelT\n WyV4P1wCsZMWFm7DM2nb88i908TxhiGuYEElSEi1uFQOFnGbR6chk6DTc\n 01ZvRkjIBygoUVa27t2Auogv5nFWuoakN+Z36WkCOpnPmQ6dSAmBo1LDW\n ahCE8j1LqU7iPHEwSU63muiQPpPPzXWopAjf57EW0bzV0hWjlGXIZ3i9F\n YZgF/sTnMzdNf8iDYsbLHfEd3jaaJgaoe8fOByWSH4xAKqfXJNxDOE8Pt\n JszMALQds7MePT7wgbzrsWJew5vnw+82w2OZQKcyoyzghvEK1NBbu38rw\n w==;","X-Mailman-Original-Authentication-Results":["smtp1.osuosl.org;\n dmarc=pass (p=none dis=none)\n header.from=intel.com","smtp1.osuosl.org;\n dkim=pass (2048-bit key,\n unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256\n header.s=Intel header.b=OrcoPhrW"],"Subject":"[Intel-wired-lan] [PATCH iwl-next v3] ice: add 200G_AUI8 PHY type\n definitions and wire them up","X-BeenThere":"intel-wired-lan@osuosl.org","X-Mailman-Version":"2.1.30","Precedence":"list","List-Id":"Intel Wired Ethernet Linux Kernel Driver Development\n ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"intel-wired-lan-bounces@osuosl.org","Sender":"\"Intel-wired-lan\" "},"content":"ice_link_mode_str_high[] lacks entries for phy_type_high bits 5-14\n(all 200G PHY types on E825C); ice_dump_phy_type() prints nothing for\nthem when ICE_DBG_LINK is set (e.g. 'ethtool -s ethX msglvl 0x10').\nThe loop also iterates all 64 bits against a 5-entry array - undefined\nbehaviour for any matched bit beyond the end. Add strings for bits\n5-14 and guard the loop with ARRAY_SIZE(), falling back to \"unknown\"\nfor unrecognised bits.\n\nICE_PHY_TYPE_HIGH_200G_AUI8_AOC_ACC (bit 13) and 200G_AUI8 (bit 14)\nwere absent from ice_adminq_cmd.h; ICE_PHY_TYPE_HIGH_MAX_INDEX capped\nat 12 caused ice_update_phy_type() to skip them entirely, leaving both\ninvisible to 200G speed requests. Add the definitions and bump\nMAX_INDEX to 14.\n\nWire the two new types throughout the driver:\n- ice_get_media_type(): handle all ten 200G phy_type_high values so\n E825C ports no longer return ICE_MEDIA_UNKNOWN. AOC_ACC interfaces\n map to FIBER; bare AUI4/AUI8 to DA with cage, else BACKPLANE\n (matching existing AUI2/CAUI2 logic); CR4_PAM4 to DA; SR4/FR4/LR4/\n DR4 to FIBER; KR4_PAM4 to BACKPLANE.\n- ice_get_link_speed_based_on_phy_type(): return ICE_AQ_LINK_SPEED_200GB\n for both new types so ice_update_phy_type() enables them correctly.\n- phy_type_high_lkup[13,14]: AUI8 is 8-lane 25G-per-lane; no\n 200000baseSR8/CR8 ethtool modes exist yet, so approximate with\n SR4_Full/CR4_Full - matching AUI4 at indices 11-12. FIXME once\n those link modes land upstream.\n- ICE_PHY_TYPE_HIGH_MASK_200G: add bits 13-14 for the minimum-speed\n floor in ice_mask_min_supported_speeds().\n\nSuggested-by: Paul Greenwalt \nSigned-off-by: Aleksandr Loktionov \nCc: Simon Horman \nCc: Paul Menzel \n---\nv3 -> v4: add ARRAY_SIZE() OOB guard in ice_dump_phy_type(); cover all\n ten 200G phy_type_high values in ice_get_media_type(); add FIXME\n to lkup[13..14] for missing SR8/CR8 modes; rename subject\n fix subject; fix debug enable example (ethtool, not modprobe);\n add AUI8 speed mapping, lkup[13-14], MASK_200G bits 13-14,\n and AUI8->SR4/CR4 approximation comment\nv1 -> v2: add ICE_PHY_TYPE_HIGH_MAX_INDEX update\n---\n .../net/ethernet/intel/ice/ice_adminq_cmd.h | 4 ++-\n drivers/net/ethernet/intel/ice/ice_common.c | 31 ++++++++++++++++++-\n drivers/net/ethernet/intel/ice/ice_ethtool.c | 4 ++-\n drivers/net/ethernet/intel/ice/ice_ethtool.h | 8 +++++\n 4 files changed, 44 insertions(+), 3 deletions(-)","diff":"diff --git a/drivers/net/ethernet/intel/ice/ice_adminq_cmd.h b/drivers/net/ethernet/intel/ice/ice_adminq_cmd.h\nindex 859e9c6..efe985c 100644\n--- a/drivers/net/ethernet/intel/ice/ice_adminq_cmd.h\n+++ b/drivers/net/ethernet/intel/ice/ice_adminq_cmd.h\n@@ -1044,7 +1044,9 @@ struct ice_aqc_get_phy_caps {\n #define ICE_PHY_TYPE_HIGH_200G_KR4_PAM4\t\tBIT_ULL(10)\n #define ICE_PHY_TYPE_HIGH_200G_AUI4_AOC_ACC\tBIT_ULL(11)\n #define ICE_PHY_TYPE_HIGH_200G_AUI4\t\tBIT_ULL(12)\n-#define ICE_PHY_TYPE_HIGH_MAX_INDEX\t\t12\n+#define ICE_PHY_TYPE_HIGH_200G_AUI8_AOC_ACC\tBIT_ULL(13)\n+#define ICE_PHY_TYPE_HIGH_200G_AUI8\t\tBIT_ULL(14)\n+#define ICE_PHY_TYPE_HIGH_MAX_INDEX\t\t14\n \n struct ice_aqc_get_phy_caps_data {\n \t__le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */\ndiff --git a/drivers/net/ethernet/intel/ice/ice_common.c b/drivers/net/ethernet/intel/ice/ice_common.c\nindex ce11fea..2f3a268 100644\n--- a/drivers/net/ethernet/intel/ice/ice_common.c\n+++ b/drivers/net/ethernet/intel/ice/ice_common.c\n@@ -84,6 +84,16 @@ static const char * const ice_link_mode_str_high[] = {\n \t[2] = \"100G_CAUI2\",\n \t[3] = \"100G_AUI2_AOC_ACC\",\n \t[4] = \"100G_AUI2\",\n+\t[5] = \"200G_CR4_PAM4\",\n+\t[6] = \"200G_SR4\",\n+\t[7] = \"200G_FR4\",\n+\t[8] = \"200G_LR4\",\n+\t[9] = \"200G_DR4\",\n+\t[10] = \"200G_KR4_PAM4\",\n+\t[11] = \"200G_AUI4_AOC_ACC\",\n+\t[12] = \"200G_AUI4\",\n+\t[13] = \"200G_AUI8_AOC_ACC\",\n+\t[14] = \"200G_AUI8\",\n };\n \n /**\n@@ -107,9 +117,14 @@ ice_dump_phy_type(struct ice_hw *hw, u64 low, u64 high, const char *prefix)\n \tice_debug(hw, ICE_DBG_PHY, \"%s: phy_type_high: 0x%016llx\\n\", prefix, high);\n \n \tfor (u32 i = 0; i < BITS_PER_TYPE(typeof(high)); i++) {\n-\t\tif (high & BIT_ULL(i))\n+\t\tif (!(high & BIT_ULL(i)))\n+\t\t\tcontinue;\n+\t\tif (i < ARRAY_SIZE(ice_link_mode_str_high))\n \t\t\tice_debug(hw, ICE_DBG_PHY, \"%s: bit(%d): %s\\n\",\n \t\t\t\t prefix, i, ice_link_mode_str_high[i]);\n+\t\telse\n+\t\t\tice_debug(hw, ICE_DBG_PHY, \"%s: bit(%d): unknown\\n\",\n+\t\t\t\t prefix, i);\n \t}\n }\n \n@@ -605,13 +620,25 @@ static enum ice_media_type ice_get_media_type(struct ice_port_info *pi)\n \t\tswitch (hw_link_info->phy_type_high) {\n \t\tcase ICE_PHY_TYPE_HIGH_100G_AUI2:\n \t\tcase ICE_PHY_TYPE_HIGH_100G_CAUI2:\n+\t\tcase ICE_PHY_TYPE_HIGH_200G_AUI4:\n+\t\tcase ICE_PHY_TYPE_HIGH_200G_AUI8:\n \t\t\tif (ice_is_media_cage_present(pi))\n \t\t\t\treturn ICE_MEDIA_DA;\n \t\t\tfallthrough;\n \t\tcase ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4:\n+\t\tcase ICE_PHY_TYPE_HIGH_200G_KR4_PAM4:\n \t\t\treturn ICE_MEDIA_BACKPLANE;\n \t\tcase ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC:\n \t\tcase ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC:\n+\t\tcase ICE_PHY_TYPE_HIGH_200G_AUI4_AOC_ACC:\n+\t\tcase ICE_PHY_TYPE_HIGH_200G_AUI8_AOC_ACC:\n+\t\t\treturn ICE_MEDIA_FIBER;\n+\t\tcase ICE_PHY_TYPE_HIGH_200G_CR4_PAM4:\n+\t\t\treturn ICE_MEDIA_DA;\n+\t\tcase ICE_PHY_TYPE_HIGH_200G_SR4:\n+\t\tcase ICE_PHY_TYPE_HIGH_200G_FR4:\n+\t\tcase ICE_PHY_TYPE_HIGH_200G_LR4:\n+\t\tcase ICE_PHY_TYPE_HIGH_200G_DR4:\n \t\t\treturn ICE_MEDIA_FIBER;\n \t\t}\n \t}\n@@ -3493,6 +3520,8 @@ u16 ice_get_link_speed_based_on_phy_type(u64 phy_type_low, u64 phy_type_high)\n \tcase ICE_PHY_TYPE_HIGH_200G_KR4_PAM4:\n \tcase ICE_PHY_TYPE_HIGH_200G_AUI4_AOC_ACC:\n \tcase ICE_PHY_TYPE_HIGH_200G_AUI4:\n+\tcase ICE_PHY_TYPE_HIGH_200G_AUI8_AOC_ACC:\n+\tcase ICE_PHY_TYPE_HIGH_200G_AUI8:\n \t\tspeed_phy_type_high = ICE_AQ_LINK_SPEED_200GB;\n \t\tbreak;\n \tdefault:\ndiff --git a/drivers/net/ethernet/intel/ice/ice_ethtool.c b/drivers/net/ethernet/intel/ice/ice_ethtool.c\nindex 301947d..beb638c 100644\n--- a/drivers/net/ethernet/intel/ice/ice_ethtool.c\n+++ b/drivers/net/ethernet/intel/ice/ice_ethtool.c\n@@ -2057,7 +2057,9 @@ ice_get_ethtool_stats(struct net_device *netdev,\n \t\t\t\t\t ICE_PHY_TYPE_HIGH_200G_DR4 | \\\n \t\t\t\t\t ICE_PHY_TYPE_HIGH_200G_KR4_PAM4 | \\\n \t\t\t\t\t ICE_PHY_TYPE_HIGH_200G_AUI4_AOC_ACC | \\\n-\t\t\t\t\t ICE_PHY_TYPE_HIGH_200G_AUI4)\n+\t\t\t\t\t ICE_PHY_TYPE_HIGH_200G_AUI4 | \\\n+\t\t\t\t\t ICE_PHY_TYPE_HIGH_200G_AUI8_AOC_ACC | \\\n+\t\t\t\t\t ICE_PHY_TYPE_HIGH_200G_AUI8)\n \n /**\n * ice_mask_min_supported_speeds\ndiff --git a/drivers/net/ethernet/intel/ice/ice_ethtool.h b/drivers/net/ethernet/intel/ice/ice_ethtool.h\nindex 23b2cfb..c4732a3 100644\n--- a/drivers/net/ethernet/intel/ice/ice_ethtool.h\n+++ b/drivers/net/ethernet/intel/ice/ice_ethtool.h\n@@ -153,6 +153,14 @@ phy_type_high_lkup[] = {\n \t[10] = ICE_PHY_TYPE(200GB, 200000baseKR4_Full),\n \t[11] = ICE_PHY_TYPE(200GB, 200000baseSR4_Full),\n \t[12] = ICE_PHY_TYPE(200GB, 200000baseCR4_Full),\n+\t/* 200G_AUI8_AOC_ACC and 200G_AUI8 are 8-lane 25G-per-lane interfaces.\n+\t * The kernel has no 200000baseSR8/CR8 modes yet; map to the closest\n+\t * available 4-lane equivalents so ethtool reports 200G as supported.\n+\t * FIXME: replace with 200000baseSR8_Full / 200000baseCR8_Full once\n+\t * those ethtool link modes are defined upstream.\n+\t */\n+\t[13] = ICE_PHY_TYPE(200GB, 200000baseSR4_Full),\n+\t[14] = ICE_PHY_TYPE(200GB, 200000baseCR4_Full),\n };\n \n #endif /* !_ICE_ETHTOOL_H_ */\n","prefixes":["iwl-next","v3"]}