{"id":2215430,"url":"http://patchwork.ozlabs.org/api/patches/2215430/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260324151323.74473-13-mohamed@unpredictable.fr/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260324151323.74473-13-mohamed@unpredictable.fr>","list_archive_url":null,"date":"2026-03-24T15:13:23","name":"[v3,12/12] whpx: i386: fast runtime state reads","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"99d2735d9405552e1a7d9af607c891556520e494","submitter":{"id":91318,"url":"http://patchwork.ozlabs.org/api/people/91318/?format=json","name":"Mohamed Mediouni","email":"mohamed@unpredictable.fr"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260324151323.74473-13-mohamed@unpredictable.fr/mbox/","series":[{"id":497303,"url":"http://patchwork.ozlabs.org/api/series/497303/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=497303","date":"2026-03-24T15:13:13","name":"whpx: i386: Windows 10 and performance fixes","version":3,"mbox":"http://patchwork.ozlabs.org/series/497303/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2215430/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2215430/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=unpredictable.fr header.i=@unpredictable.fr\n header.a=rsa-sha256 header.s=sig1 header.b=dnuuG0Yo;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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helo=outbound.st.icloud.com","X-Spam_score_int":"-27","X-Spam_score":"-2.8","X-Spam_bar":"--","X-Spam_report":"(-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001,\n RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_PASS=-0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"Now that there's an on-demand interface for fetching CRs\nand segments, only query GPRs and query everything else\non-demand for vmexits.\n\nSigned-off-by: Mohamed Mediouni \n---\n target/i386/whpx/whpx-all.c | 77 +++++++++++++++++++++++++++++++++----\n 1 file changed, 70 insertions(+), 7 deletions(-)","diff":"diff --git a/target/i386/whpx/whpx-all.c b/target/i386/whpx/whpx-all.c\nindex 6f23278642..acae61e089 100644\n--- a/target/i386/whpx/whpx-all.c\n+++ b/target/i386/whpx/whpx-all.c\n@@ -156,6 +156,26 @@ static const WHV_REGISTER_NAME whpx_register_names[] = {\n */\n };\n \n+static const WHV_REGISTER_NAME whpx_register_names_for_vmexit[] = {\n+ /* X64 General purpose registers */\n+ WHvX64RegisterRax,\n+ WHvX64RegisterRcx,\n+ WHvX64RegisterRdx,\n+ WHvX64RegisterRbx,\n+ WHvX64RegisterRsp,\n+ WHvX64RegisterRbp,\n+ WHvX64RegisterRsi,\n+ WHvX64RegisterRdi,\n+ WHvX64RegisterR8,\n+ WHvX64RegisterR9,\n+ WHvX64RegisterR10,\n+ WHvX64RegisterR11,\n+ WHvX64RegisterR12,\n+ WHvX64RegisterR13,\n+ WHvX64RegisterR14,\n+ WHvX64RegisterR15,\n+};\n+\n struct whpx_register_set {\n WHV_REGISTER_VALUE values[RTL_NUMBER_OF(whpx_register_names)];\n };\n@@ -593,6 +613,47 @@ static void whpx_get_xcrs(CPUState *cpu)\n cpu_env(cpu)->xcr0 = xcr0.Reg64;\n }\n \n+static void whpx_get_registers_for_vmexit(CPUState *cpu, WHPXStateLevel level)\n+{\n+ struct whpx_state *whpx = &whpx_global;\n+ AccelCPUState *vcpu = cpu->accel;\n+ X86CPU *x86_cpu = X86_CPU(cpu);\n+ CPUX86State *env = &x86_cpu->env;\n+ struct whpx_register_set vcxt;\n+ HRESULT hr;\n+ int idx;\n+ int idx_next;\n+\n+ assert(cpu_is_stopped(cpu) || qemu_cpu_is_self(cpu));\n+\n+ hr = whp_dispatch.WHvGetVirtualProcessorRegisters(\n+ whpx->partition, cpu->cpu_index,\n+ whpx_register_names_for_vmexit,\n+ RTL_NUMBER_OF(whpx_register_names_for_vmexit),\n+ &vcxt.values[0]);\n+ if (FAILED(hr)) {\n+ error_report(\"WHPX: Failed to get virtual processor context, hr=%08lx\",\n+ hr);\n+ }\n+\n+ idx = 0;\n+\n+ /* Indexes for first 16 registers match between HV and QEMU definitions */\n+ idx_next = 16;\n+ for (idx = 0; idx < CPU_NB_REGS; idx += 1) {\n+ env->regs[idx] = vcxt.values[idx].Reg64;\n+ }\n+ idx = idx_next;\n+\n+ env->eip = vcpu->exit_ctx.VpContext.Rip;\n+ env->eflags = vcpu->exit_ctx.VpContext.Rflags;\n+ rflags_to_lflags(env);\n+\n+ assert(idx == RTL_NUMBER_OF(whpx_register_names_for_vmexit));\n+\n+ x86_update_hflags(env);\n+}\n+\n void whpx_get_registers(CPUState *cpu, WHPXStateLevel level)\n {\n struct whpx_state *whpx = &whpx_global;\n@@ -608,7 +669,11 @@ void whpx_get_registers(CPUState *cpu, WHPXStateLevel level)\n \n assert(cpu_is_stopped(cpu) || qemu_cpu_is_self(cpu));\n \n- if (level > WHPX_LEVEL_FAST_RUNTIME_STATE && !env->tsc_valid) {\n+ if (level == WHPX_LEVEL_FAST_RUNTIME_STATE) {\n+ return whpx_get_registers_for_vmexit(cpu, level);\n+ }\n+\n+ if (!env->tsc_valid) {\n whpx_get_tsc(cpu);\n env->tsc_valid = !runstate_is_running();\n }\n@@ -623,7 +688,7 @@ void whpx_get_registers(CPUState *cpu, WHPXStateLevel level)\n hr);\n }\n \n- if (level > WHPX_LEVEL_FAST_RUNTIME_STATE && whpx_irqchip_in_kernel()) {\n+ if (whpx_irqchip_in_kernel()) {\n /*\n * Fetch the TPR value from the emulated APIC. It may get overwritten\n * below with the value from CR8 returned by\n@@ -680,7 +745,7 @@ void whpx_get_registers(CPUState *cpu, WHPXStateLevel level)\n env->cr[4] = vcxt.values[idx++].Reg64;\n assert(whpx_register_names[idx] == WHvX64RegisterCr8);\n tpr = vcxt.values[idx++].Reg64;\n- if (level > WHPX_LEVEL_FAST_RUNTIME_STATE && tpr != vcpu->tpr) {\n+ if (tpr != vcpu->tpr) {\n vcpu->tpr = tpr;\n cpu_set_apic_tpr(x86_cpu->apic_state, whpx_cr8_to_apic_tpr(tpr));\n }\n@@ -691,9 +756,7 @@ void whpx_get_registers(CPUState *cpu, WHPXStateLevel level)\n * Extended control registers needs to be handled separately depending\n * on whether xsave is supported/enabled or not.\n */\n- if (level > WHPX_LEVEL_FAST_RUNTIME_STATE) {\n- whpx_get_xcrs(cpu);\n- }\n+ whpx_get_xcrs(cpu);\n \n /* 16 XMM registers */\n assert(whpx_register_names[idx] == WHvX64RegisterXmm0);\n@@ -768,7 +831,7 @@ void whpx_get_registers(CPUState *cpu, WHPXStateLevel level)\n \n assert(idx == RTL_NUMBER_OF(whpx_register_names));\n \n- if (level > WHPX_LEVEL_FAST_RUNTIME_STATE && whpx_irqchip_in_kernel()) {\n+ if (whpx_irqchip_in_kernel()) {\n whpx_apic_get(x86_cpu->apic_state);\n }\n \n","prefixes":["v3","12/12"]}