{"id":2215409,"url":"http://patchwork.ozlabs.org/api/patches/2215409/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260324151111.237411-10-peter.maydell@linaro.org/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260324151111.237411-10-peter.maydell@linaro.org>","list_archive_url":null,"date":"2026-03-24T15:11:09","name":"[PULL,09/11] qdev: Add an OasMode property type","commit_ref":null,"pull_url":null,"state":"not-applicable","archived":false,"hash":"eef663d6dd200b0ebc8821f340907574feed4a6c","submitter":{"id":5111,"url":"http://patchwork.ozlabs.org/api/people/5111/?format=json","name":"Peter Maydell","email":"peter.maydell@linaro.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260324151111.237411-10-peter.maydell@linaro.org/mbox/","series":[{"id":497302,"url":"http://patchwork.ozlabs.org/api/series/497302/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=497302","date":"2026-03-24T15:11:00","name":"[PULL,01/11] target/arm: fix s2prot not set for two-stage PMSA translations","version":1,"mbox":"http://patchwork.ozlabs.org/series/497302/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2215409/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2215409/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=ADXAkpml;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from lists.gnu.org (lists.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fgD6D5PY3z1y1G\n\tfor ; Wed, 25 Mar 2026 02:12:04 +1100 (AEDT)","from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from )\n\tid 1w53Pn-0000ms-9V; Tue, 24 Mar 2026 11:11:31 -0400","from eggs.gnu.org ([2001:470:142:3::10])\n by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from )\n id 1w53Pl-0000lX-3y\n for qemu-devel@nongnu.org; Tue, 24 Mar 2026 11:11:29 -0400","from mail-wr1-x42b.google.com ([2a00:1450:4864:20::42b])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from )\n id 1w53Pj-0005E9-FS\n for qemu-devel@nongnu.org; Tue, 24 Mar 2026 11:11:28 -0400","by mail-wr1-x42b.google.com with SMTP id\n ffacd0b85a97d-439d8dc4ae4so4843460f8f.2\n for ; Tue, 24 Mar 2026 08:11:27 -0700 (PDT)","from lanath.. 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Values are auto, 32, 36, 40, 42, 44, 48, 52, and 56, where a\nvalue of N specifies an N-bit OAS.\n\nReviewed-by: Eric Auger \nTested-by: Eric Auger \nTested-by: Shameer Kolothum \nAcked-by: Markus Armbruster \nSigned-off-by: Nathan Chen \nMessage-id: 20260323182454.1416110-7-nathanc@nvidia.com\nSigned-off-by: Peter Maydell \n---\n hw/core/qdev-properties-system.c | 13 +++++++++++\n include/hw/core/qdev-properties-system.h | 3 +++\n qapi/misc-arm.json | 28 ++++++++++++++++++++++++\n 3 files changed, 44 insertions(+)","diff":"diff --git a/hw/core/qdev-properties-system.c b/hw/core/qdev-properties-system.c\nindex 4aca1d4326..a805ee2e1f 100644\n--- a/hw/core/qdev-properties-system.c\n+++ b/hw/core/qdev-properties-system.c\n@@ -737,6 +737,19 @@ const PropertyInfo qdev_prop_ssidsize_mode = {\n .set_default_value = qdev_propinfo_set_default_value_enum,\n };\n \n+/* --- OasMode --- */\n+\n+QEMU_BUILD_BUG_ON(sizeof(OasMode) != sizeof(int));\n+\n+const PropertyInfo qdev_prop_oas_mode = {\n+ .type = \"OasMode\",\n+ .description = \"oas mode: auto, 32, 36, 40, 42, 44, 48, 52, 56\",\n+ .enum_table = &OasMode_lookup,\n+ .get = qdev_propinfo_get_enum,\n+ .set = qdev_propinfo_set_enum,\n+ .set_default_value = qdev_propinfo_set_default_value_enum,\n+};\n+\n /* --- Reserved Region --- */\n \n /*\ndiff --git a/include/hw/core/qdev-properties-system.h b/include/hw/core/qdev-properties-system.h\nindex 4708885164..2cbea16d61 100644\n--- a/include/hw/core/qdev-properties-system.h\n+++ b/include/hw/core/qdev-properties-system.h\n@@ -15,6 +15,7 @@ extern const PropertyInfo qdev_prop_mig_mode;\n extern const PropertyInfo qdev_prop_granule_mode;\n extern const PropertyInfo qdev_prop_zero_page_detection;\n extern const PropertyInfo qdev_prop_ssidsize_mode;\n+extern const PropertyInfo qdev_prop_oas_mode;\n extern const PropertyInfo qdev_prop_losttickpolicy;\n extern const PropertyInfo qdev_prop_blockdev_on_error;\n extern const PropertyInfo qdev_prop_bios_chs_trans;\n@@ -64,6 +65,8 @@ extern const PropertyInfo qdev_prop_virtio_gpu_output_list;\n ZeroPageDetection)\n #define DEFINE_PROP_SSIDSIZE_MODE(_n, _s, _f, _d) \\\n DEFINE_PROP_SIGNED(_n, _s, _f, _d, qdev_prop_ssidsize_mode, SsidSizeMode)\n+#define DEFINE_PROP_OAS_MODE(_n, _s, _f, _d) \\\n+ DEFINE_PROP_SIGNED(_n, _s, _f, _d, qdev_prop_oas_mode, OasMode)\n #define DEFINE_PROP_LOSTTICKPOLICY(_n, _s, _f, _d) \\\n DEFINE_PROP_SIGNED(_n, _s, _f, _d, qdev_prop_losttickpolicy, \\\n LostTickPolicy)\ndiff --git a/qapi/misc-arm.json b/qapi/misc-arm.json\nindex 416b4240e2..4dc66d00e5 100644\n--- a/qapi/misc-arm.json\n+++ b/qapi/misc-arm.json\n@@ -61,3 +61,31 @@\n 'data': [ 'auto', '0', '1', '2', '3', '4', '5', '6', '7', '8', '9',\n '10', '11', '12', '13', '14', '15', '16', '17', '18',\n '19', '20' ] } # order matters, see ssidsize_mode_to_value()\n+\n+##\n+# @OasMode:\n+#\n+# SMMUv3 Output Address Size configuration mode.\n+#\n+# @auto: derive from host IOMMU capabilities\n+#\n+# @32: 32-bit output address size\n+#\n+# @36: 36-bit output address size\n+#\n+# @40: 40-bit output address size\n+#\n+# @42: 42-bit output address size\n+#\n+# @44: 44-bit output address size\n+#\n+# @48: 48-bit output address size\n+#\n+# @52: 52-bit output address size\n+#\n+# @56: 56-bit output address size\n+#\n+# Since: 11.0\n+##\n+{ 'enum': 'OasMode',\n+ 'data': [ 'auto', '32', '36', '40', '42', '44', '48', '52', '56' ] }\n","prefixes":["PULL","09/11"]}