{"id":2215408,"url":"http://patchwork.ozlabs.org/api/patches/2215408/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260324151111.237411-9-peter.maydell@linaro.org/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260324151111.237411-9-peter.maydell@linaro.org>","list_archive_url":null,"date":"2026-03-24T15:11:08","name":"[PULL,08/11] hw/arm/smmuv3-accel: Change \"ssidsize\" property type to SsidSizeMode","commit_ref":null,"pull_url":null,"state":"not-applicable","archived":false,"hash":"dd31e3d58d61e71965c503ec1dc5b305019fb8ab","submitter":{"id":5111,"url":"http://patchwork.ozlabs.org/api/people/5111/?format=json","name":"Peter Maydell","email":"peter.maydell@linaro.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260324151111.237411-9-peter.maydell@linaro.org/mbox/","series":[{"id":497302,"url":"http://patchwork.ozlabs.org/api/series/497302/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=497302","date":"2026-03-24T15:11:00","name":"[PULL,01/11] target/arm: fix s2prot not set for two-stage PMSA translations","version":1,"mbox":"http://patchwork.ozlabs.org/series/497302/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2215408/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2215408/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=Kq0kaArP;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from lists.gnu.org (lists.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fgD62257Nz1y1G\n\tfor ; Wed, 25 Mar 2026 02:11:54 +1100 (AEDT)","from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from )\n\tid 1w53Pw-0000tv-6w; Tue, 24 Mar 2026 11:11:41 -0400","from eggs.gnu.org ([2001:470:142:3::10])\n by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from )\n id 1w53Pj-0000jn-QF\n for qemu-devel@nongnu.org; Tue, 24 Mar 2026 11:11:27 -0400","from mail-wm1-x32f.google.com ([2a00:1450:4864:20::32f])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from )\n id 1w53Ph-0005Do-QD\n for qemu-devel@nongnu.org; Tue, 24 Mar 2026 11:11:27 -0400","by mail-wm1-x32f.google.com with SMTP id\n 5b1f17b1804b1-486b96760easo12859155e9.2\n for ; Tue, 24 Mar 2026 08:11:25 -0700 (PDT)","from lanath.. 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A future patch will implement resolution of 'auto'\nvalue to match the host SMMUv3 SSIDSIZE value.\n\nThe conversion of the \"ssidsize\" property type to OnOffAuto is an\nincompatible change for JSON/QMP when a uint8_t value is expected for\n\"ssidsize\", but this property is new in 11.0 and this patch is\nsubmitted as a fix to the property type.\n\nFixes: b8c6f8a69d27 (\"hw/arm/smmuv3-accel: Make SubstreamID support configurable\")\nTested-by: Eric Auger \nReviewed-by: Shameer Kolothum \nReviewed-by: Eric Auger \nTested-by: Shameer Kolothum \nAcked-by: Markus Armbruster \nSigned-off-by: Nathan Chen \nMessage-id: 20260323182454.1416110-6-nathanc@nvidia.com\nSigned-off-by: Peter Maydell \n---\n hw/arm/smmuv3-accel.c | 23 +++++++++++++++++++++--\n hw/arm/smmuv3.c | 19 ++++++++++---------\n include/hw/arm/smmuv3-common.h | 1 -\n include/hw/arm/smmuv3.h | 3 ++-\n 4 files changed, 33 insertions(+), 13 deletions(-)","diff":"diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c\nindex c31b64295e..bc6cbfebc2 100644\n--- a/hw/arm/smmuv3-accel.c\n+++ b/hw/arm/smmuv3-accel.c\n@@ -802,7 +802,7 @@ static uint64_t smmuv3_accel_get_viommu_flags(void *opaque)\n SMMUState *bs = opaque;\n SMMUv3State *s = ARM_SMMUV3(bs);\n \n- if (s->ssidsize) {\n+ if (s->ssidsize > SSID_SIZE_MODE_0) {\n flags |= VIOMMU_FLAG_PASID_SUPPORTED;\n }\n return flags;\n@@ -817,6 +817,22 @@ static const PCIIOMMUOps smmuv3_accel_ops = {\n .get_msi_direct_gpa = smmuv3_accel_get_msi_gpa,\n };\n \n+/*\n+ * This returns the value of a SsidSizeMode value offset by 1 to\n+ * account for the enum values offset by 1 from actual values.\n+ *\n+ * SSID_SIZE_MODE_0 = 1, SSID_SIZE_MODE_1 = 2, etc. so return 0\n+ * if SSID_SIZE_MODE_0 is passed as input, return 1 if\n+ * SSID_SIZE_MODE_1 is passed as input, etc.\n+ */\n+static uint8_t ssidsize_mode_to_value(SsidSizeMode mode)\n+{\n+ if (mode == SSID_SIZE_MODE_AUTO) {\n+ return 0;\n+ }\n+ return mode - 1;\n+}\n+\n void smmuv3_accel_idr_override(SMMUv3State *s)\n {\n if (!s->accel) {\n@@ -842,7 +858,10 @@ void smmuv3_accel_idr_override(SMMUv3State *s)\n * By default QEMU SMMUv3 has no SubstreamID support. Update IDR1 if user\n * has enabled it.\n */\n- s->idr[1] = FIELD_DP32(s->idr[1], IDR1, SSIDSIZE, s->ssidsize);\n+ if (s->ssidsize > SSID_SIZE_MODE_0) {\n+ s->idr[1] = FIELD_DP32(s->idr[1], IDR1, SSIDSIZE,\n+ ssidsize_mode_to_value(s->ssidsize));\n+ }\n }\n \n /* Based on SMUUv3 GPBA.ABORT configuration, attach a corresponding HWPT */\ndiff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c\nindex ea285bdf64..79018f8d66 100644\n--- a/hw/arm/smmuv3.c\n+++ b/hw/arm/smmuv3.c\n@@ -20,6 +20,7 @@\n #include \"qemu/bitops.h\"\n #include \"hw/core/irq.h\"\n #include \"hw/core/sysbus.h\"\n+#include \"hw/core/qdev-properties-system.h\"\n #include \"migration/blocker.h\"\n #include \"migration/vmstate.h\"\n #include \"hw/core/qdev-properties.h\"\n@@ -625,7 +626,7 @@ static int decode_ste(SMMUv3State *s, SMMUTransCfg *cfg,\n }\n \n /* Multiple context descriptors require SubstreamID support */\n- if (!s->ssidsize && STE_S1CDMAX(ste) != 0) {\n+ if (s->ssidsize == SSID_SIZE_MODE_0 && STE_S1CDMAX(ste) != 0) {\n qemu_log_mask(LOG_UNIMP,\n \"SMMUv3: multiple S1 context descriptors require SubstreamID support. \"\n \"Configure ssidsize > 0 (requires accel=on)\\n\");\n@@ -1979,6 +1980,10 @@ static bool smmu_validate_property(SMMUv3State *s, Error **errp)\n error_setg(errp, \"ril auto mode is not supported\");\n return false;\n }\n+ if (s->ssidsize == SSID_SIZE_MODE_AUTO) {\n+ error_setg(errp, \"ssidsize auto mode is not supported\");\n+ return false;\n+ }\n \n if (!s->accel) {\n if (s->ril == ON_OFF_AUTO_OFF) {\n@@ -1993,7 +1998,7 @@ static bool smmu_validate_property(SMMUv3State *s, Error **errp)\n error_setg(errp, \"OAS must be 44 bits when accel=off\");\n return false;\n }\n- if (s->ssidsize) {\n+ if (s->ssidsize > SSID_SIZE_MODE_0) {\n error_setg(errp, \"ssidsize can only be set if accel=on\");\n return false;\n }\n@@ -2011,11 +2016,6 @@ static bool smmu_validate_property(SMMUv3State *s, Error **errp)\n error_setg(errp, \"OAS can only be set to 44 or 48 bits\");\n return false;\n }\n- if (s->ssidsize > SMMU_SSID_MAX_BITS) {\n- error_setg(errp, \"ssidsize must be in the range 0 to %d\",\n- SMMU_SSID_MAX_BITS);\n- return false;\n- }\n \n return true;\n }\n@@ -2144,7 +2144,8 @@ static const Property smmuv3_properties[] = {\n DEFINE_PROP_ON_OFF_AUTO(\"ril\", SMMUv3State, ril, ON_OFF_AUTO_ON),\n DEFINE_PROP_ON_OFF_AUTO(\"ats\", SMMUv3State, ats, ON_OFF_AUTO_OFF),\n DEFINE_PROP_UINT8(\"oas\", SMMUv3State, oas, 44),\n- DEFINE_PROP_UINT8(\"ssidsize\", SMMUv3State, ssidsize, 0),\n+ DEFINE_PROP_SSIDSIZE_MODE(\"ssidsize\", SMMUv3State, ssidsize,\n+ SSID_SIZE_MODE_0),\n };\n \n static void smmuv3_instance_init(Object *obj)\n@@ -2185,7 +2186,7 @@ static void smmuv3_class_init(ObjectClass *klass, const void *data)\n \"A value of N allows SSIDs in the range [0 .. 2^N - 1]. \"\n \"Valid range is 0-20, where 0 disables SubstreamID support. \"\n \"Defaults to 0. A value greater than 0 is required to enable \"\n- \"PASID support.\");\n+ \"PASID support. ssidsize=auto is not supported.\");\n }\n \n static int smmuv3_notify_flag_changed(IOMMUMemoryRegion *iommu,\ndiff --git a/include/hw/arm/smmuv3-common.h b/include/hw/arm/smmuv3-common.h\nindex 9f78bbe89e..7f0f992dfd 100644\n--- a/include/hw/arm/smmuv3-common.h\n+++ b/include/hw/arm/smmuv3-common.h\n@@ -311,7 +311,6 @@ REG32(IDR1, 0x4)\n FIELD(IDR1, TABLES_PRESET, 30, 1)\n FIELD(IDR1, ECMDQ, 31, 1)\n \n-#define SMMU_SSID_MAX_BITS 20\n #define SMMU_IDR1_SIDSIZE 16\n #define SMMU_CMDQS 19\n #define SMMU_EVENTQS 19\ndiff --git a/include/hw/arm/smmuv3.h b/include/hw/arm/smmuv3.h\nindex c35e599bbc..ddf472493d 100644\n--- a/include/hw/arm/smmuv3.h\n+++ b/include/hw/arm/smmuv3.h\n@@ -21,6 +21,7 @@\n \n #include \"hw/arm/smmu-common.h\"\n #include \"qom/object.h\"\n+#include \"qapi/qapi-types-misc-arm.h\"\n \n #define TYPE_SMMUV3_IOMMU_MEMORY_REGION \"smmuv3-iommu-memory-region\"\n \n@@ -72,7 +73,7 @@ struct SMMUv3State {\n OnOffAuto ril;\n OnOffAuto ats;\n uint8_t oas;\n- uint8_t ssidsize;\n+ SsidSizeMode ssidsize;\n };\n \n typedef enum {\n","prefixes":["PULL","08/11"]}