{"id":2137019,"url":"http://patchwork.ozlabs.org/api/patches/2137019/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-tegra/patch/20250915080157.28195-5-clamor95@gmail.com/","project":{"id":21,"url":"http://patchwork.ozlabs.org/api/projects/21/?format=json","name":"Linux Tegra Development","link_name":"linux-tegra","list_id":"linux-tegra.vger.kernel.org","list_email":"linux-tegra@vger.kernel.org","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20250915080157.28195-5-clamor95@gmail.com>","list_archive_url":null,"date":"2025-09-15T08:01:50","name":"[v3,04/11] memory: tegra: implement EMEM regs and ICC ops for Tegra114","commit_ref":null,"pull_url":null,"state":"changes-requested","archived":false,"hash":"7826f0e37391779cdcd00485605163c11a77528e","submitter":{"id":84146,"url":"http://patchwork.ozlabs.org/api/people/84146/?format=json","name":"Svyatoslav Ryhel","email":"clamor95@gmail.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/linux-tegra/patch/20250915080157.28195-5-clamor95@gmail.com/mbox/","series":[{"id":473640,"url":"http://patchwork.ozlabs.org/api/series/473640/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-tegra/list/?series=473640","date":"2025-09-15T08:01:46","name":"Tegra114: implement EMC support","version":3,"mbox":"http://patchwork.ozlabs.org/series/473640/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2137019/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2137019/checks/","tags":{},"related":[],"headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-tegra@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20230601 header.b=DosSW2gp;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=139.178.88.99; helo=sv.mirrors.kernel.org;\n envelope-from=linux-tegra+bounces-9249-incoming=patchwork.ozlabs.org@vger.kernel.org;\n receiver=patchwork.ozlabs.org)","smtp.subspace.kernel.org;\n\tdkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com\n header.b=\"DosSW2gp\"","smtp.subspace.kernel.org;\n arc=none smtp.client-ip=209.85.167.53","smtp.subspace.kernel.org;\n dmarc=pass (p=none dis=none) header.from=gmail.com","smtp.subspace.kernel.org;\n spf=pass smtp.mailfrom=gmail.com"],"Received":["from sv.mirrors.kernel.org (sv.mirrors.kernel.org [139.178.88.99])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange X25519 server-signature ECDSA (secp384r1))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4cQHZK4XsDz1y1Y\n\tfor ; Mon, 15 Sep 2025 18:02:33 +1000 (AEST)","from smtp.subspace.kernel.org (relay.kernel.org [52.25.139.140])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby sv.mirrors.kernel.org (Postfix) with ESMTPS id 27C2B3ADF56\n\tfor ; Mon, 15 Sep 2025 08:02:32 +0000 (UTC)","from localhost.localdomain (localhost.localdomain [127.0.0.1])\n\tby smtp.subspace.kernel.org (Postfix) with ESMTP id CC3312EC092;\n\tMon, 15 Sep 2025 08:02:31 +0000 (UTC)","from mail-lf1-f53.google.com (mail-lf1-f53.google.com\n [209.85.167.53])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits))\n\t(No client certificate requested)\n\tby smtp.subspace.kernel.org (Postfix) with ESMTPS id 4E9302EBB8A\n\tfor ; Mon, 15 Sep 2025 08:02:29 +0000 (UTC)","by mail-lf1-f53.google.com with SMTP id\n 2adb3069b0e04-55f7ab2a84eso3684926e87.1\n for ;\n Mon, 15 Sep 2025 01:02:29 -0700 (PDT)","from xeon.. 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All rights reserved.\n */\n \n+#include \n #include \n #include \n \n@@ -1165,6 +1166,195 @@ static const struct tegra_mc_reset tegra114_mc_resets[] = {\n \tTEGRA114_MC_RESET(VI, 0x200, 0x204, 17),\n };\n \n+static void tegra114_mc_tune_client_latency(struct tegra_mc *mc,\n+\t\t\t\t\t const struct tegra_mc_client *client,\n+\t\t\t\t\t unsigned int bandwidth_mbytes_sec)\n+{\n+\tu32 arb_tolerance_compensation_nsec, arb_tolerance_compensation_div;\n+\tunsigned int fifo_size = client->fifo_size;\n+\tu32 arb_nsec, la_ticks, value;\n+\n+\t/* see 20.3.1.1 Client Configuration in Tegra4 TRM v01p */\n+\tif (bandwidth_mbytes_sec)\n+\t\tarb_nsec = fifo_size * NSEC_PER_USEC / bandwidth_mbytes_sec;\n+\telse\n+\t\tarb_nsec = U32_MAX;\n+\n+\t/*\n+\t * Latency allowness should be set with consideration for the module's\n+\t * latency tolerance and internal buffering capabilities.\n+\t *\n+\t * Display memory clients use isochronous transfers and have very low\n+\t * tolerance to a belated transfers. Hence we need to compensate the\n+\t * memory arbitration imperfection for them in order to prevent FIFO\n+\t * underflow condition when memory bus is busy.\n+\t *\n+\t * VI clients also need a stronger compensation.\n+\t */\n+\tswitch (client->swgroup) {\n+\tcase TEGRA_SWGROUP_MPCORE:\n+\tcase TEGRA_SWGROUP_PTC:\n+\t\t/*\n+\t\t * We always want lower latency for these clients, hence\n+\t\t * don't touch them.\n+\t\t */\n+\t\treturn;\n+\n+\tcase TEGRA_SWGROUP_DC:\n+\tcase TEGRA_SWGROUP_DCB:\n+\t\tarb_tolerance_compensation_nsec = 1050;\n+\t\tarb_tolerance_compensation_div = 2;\n+\t\tbreak;\n+\n+\tcase TEGRA_SWGROUP_VI:\n+\t\tarb_tolerance_compensation_nsec = 1050;\n+\t\tarb_tolerance_compensation_div = 1;\n+\t\tbreak;\n+\n+\tdefault:\n+\t\tarb_tolerance_compensation_nsec = 150;\n+\t\tarb_tolerance_compensation_div = 1;\n+\t\tbreak;\n+\t}\n+\n+\tif (arb_nsec > arb_tolerance_compensation_nsec)\n+\t\tarb_nsec -= arb_tolerance_compensation_nsec;\n+\telse\n+\t\tarb_nsec = 0;\n+\n+\tarb_nsec /= arb_tolerance_compensation_div;\n+\n+\t/*\n+\t * Latency allowance is a number of ticks a request from a particular\n+\t * client may wait in the EMEM arbiter before it becomes a high-priority\n+\t * request.\n+\t */\n+\tla_ticks = arb_nsec / mc->tick;\n+\tla_ticks = min(la_ticks, client->regs.la.mask);\n+\n+\tvalue = mc_readl(mc, client->regs.la.reg);\n+\tvalue &= ~(client->regs.la.mask << client->regs.la.shift);\n+\tvalue |= la_ticks << client->regs.la.shift;\n+\tmc_writel(mc, value, client->regs.la.reg);\n+}\n+\n+static int tegra114_mc_icc_set(struct icc_node *src, struct icc_node *dst)\n+{\n+\tstruct tegra_mc *mc = icc_provider_to_tegra_mc(src->provider);\n+\tconst struct tegra_mc_client *client = &mc->soc->clients[src->id];\n+\tu64 peak_bandwidth = icc_units_to_bps(src->peak_bw);\n+\n+\t/*\n+\t * Skip pre-initialization that is done by icc_node_add(), which sets\n+\t * bandwidth to maximum for all clients before drivers are loaded.\n+\t *\n+\t * This doesn't make sense for us because we don't have drivers for all\n+\t * clients and it's okay to keep configuration left from bootloader\n+\t * during boot, at least for today.\n+\t */\n+\tif (src == dst)\n+\t\treturn 0;\n+\n+\t/* convert bytes/sec to megabytes/sec */\n+\tdo_div(peak_bandwidth, 1000000);\n+\n+\ttegra114_mc_tune_client_latency(mc, client, peak_bandwidth);\n+\n+\treturn 0;\n+}\n+\n+static int tegra114_mc_icc_aggreate(struct icc_node *node, u32 tag, u32 avg_bw,\n+\t\t\t\t u32 peak_bw, u32 *agg_avg, u32 *agg_peak)\n+{\n+\t/*\n+\t * ISO clients need to reserve extra bandwidth up-front because\n+\t * there could be high bandwidth pressure during initial filling\n+\t * of the client's FIFO buffers. Secondly, we need to take into\n+\t * account impurities of the memory subsystem.\n+\t */\n+\tif (tag & TEGRA_MC_ICC_TAG_ISO)\n+\t\tpeak_bw = tegra_mc_scale_percents(peak_bw, 400);\n+\n+\t*agg_avg += avg_bw;\n+\t*agg_peak = max(*agg_peak, peak_bw);\n+\n+\treturn 0;\n+}\n+\n+static struct icc_node_data *\n+tegra114_mc_of_icc_xlate_extended(const struct of_phandle_args *spec, void *data)\n+{\n+\tstruct tegra_mc *mc = icc_provider_to_tegra_mc(data);\n+\tconst struct tegra_mc_client *client;\n+\tunsigned int i, idx = spec->args[0];\n+\tstruct icc_node_data *ndata;\n+\tstruct icc_node *node;\n+\n+\tlist_for_each_entry(node, &mc->provider.nodes, node_list) {\n+\t\tif (node->id != idx)\n+\t\t\tcontinue;\n+\n+\t\tndata = kzalloc(sizeof(*ndata), GFP_KERNEL);\n+\t\tif (!ndata)\n+\t\t\treturn ERR_PTR(-ENOMEM);\n+\n+\t\tclient = &mc->soc->clients[idx];\n+\t\tndata->node = node;\n+\n+\t\tswitch (client->swgroup) {\n+\t\tcase TEGRA_SWGROUP_DC:\n+\t\tcase TEGRA_SWGROUP_DCB:\n+\t\tcase TEGRA_SWGROUP_PTC:\n+\t\tcase TEGRA_SWGROUP_VI:\n+\t\t\t/* these clients are isochronous by default */\n+\t\t\tndata->tag = TEGRA_MC_ICC_TAG_ISO;\n+\t\t\tbreak;\n+\n+\t\tdefault:\n+\t\t\tndata->tag = TEGRA_MC_ICC_TAG_DEFAULT;\n+\t\t\tbreak;\n+\t\t}\n+\n+\t\treturn ndata;\n+\t}\n+\n+\tfor (i = 0; i < mc->soc->num_clients; i++) {\n+\t\tif (mc->soc->clients[i].id == idx)\n+\t\t\treturn ERR_PTR(-EPROBE_DEFER);\n+\t}\n+\n+\tdev_err(mc->dev, \"invalid ICC client ID %u\\n\", idx);\n+\n+\treturn ERR_PTR(-EINVAL);\n+}\n+\n+static const struct tegra_mc_icc_ops tegra114_mc_icc_ops = {\n+\t.xlate_extended = tegra114_mc_of_icc_xlate_extended,\n+\t.aggregate = tegra114_mc_icc_aggreate,\n+\t.set = tegra114_mc_icc_set,\n+};\n+\n+static const unsigned long tegra114_mc_emem_regs[] = {\n+\tMC_EMEM_ARB_CFG,\n+\tMC_EMEM_ARB_OUTSTANDING_REQ,\n+\tMC_EMEM_ARB_TIMING_RCD,\n+\tMC_EMEM_ARB_TIMING_RP,\n+\tMC_EMEM_ARB_TIMING_RC,\n+\tMC_EMEM_ARB_TIMING_RAS,\n+\tMC_EMEM_ARB_TIMING_FAW,\n+\tMC_EMEM_ARB_TIMING_RRD,\n+\tMC_EMEM_ARB_TIMING_RAP2PRE,\n+\tMC_EMEM_ARB_TIMING_WAP2PRE,\n+\tMC_EMEM_ARB_TIMING_R2R,\n+\tMC_EMEM_ARB_TIMING_W2W,\n+\tMC_EMEM_ARB_TIMING_R2W,\n+\tMC_EMEM_ARB_TIMING_W2R,\n+\tMC_EMEM_ARB_DA_TURNS,\n+\tMC_EMEM_ARB_DA_COVERS,\n+\tMC_EMEM_ARB_MISC0,\n+\tMC_EMEM_ARB_RING1_THROTTLE,\n+};\n+\n const struct tegra_mc_soc tegra114_mc_soc = {\n \t.clients = tegra114_mc_clients,\n \t.num_clients = ARRAY_SIZE(tegra114_mc_clients),\n@@ -1172,10 +1362,13 @@ const struct tegra_mc_soc tegra114_mc_soc = {\n \t.atom_size = 32,\n \t.client_id_mask = 0x7f,\n \t.smmu = &tegra114_smmu_soc,\n+\t.emem_regs = tegra114_mc_emem_regs,\n+\t.num_emem_regs = ARRAY_SIZE(tegra114_mc_emem_regs),\n \t.intmask = MC_INT_INVALID_SMMU_PAGE | MC_INT_SECURITY_VIOLATION |\n \t\t MC_INT_DECERR_EMEM,\n \t.reset_ops = &tegra_mc_reset_ops_common,\n \t.resets = tegra114_mc_resets,\n \t.num_resets = ARRAY_SIZE(tegra114_mc_resets),\n+\t.icc_ops = &tegra114_mc_icc_ops,\n \t.ops = &tegra30_mc_ops,\n };\n","prefixes":["v3","04/11"]}