{"id":2132479,"url":"http://patchwork.ozlabs.org/api/patches/2132479/?format=json","web_url":"http://patchwork.ozlabs.org/project/ubuntu-kernel/patch/f478cf354d0d94a9716986a7699b797a065ad6a1.1756973061.git.massimiliano.pellizzer@canonical.com/","project":{"id":15,"url":"http://patchwork.ozlabs.org/api/projects/15/?format=json","name":"Ubuntu Kernel","link_name":"ubuntu-kernel","list_id":"kernel-team.lists.ubuntu.com","list_email":"kernel-team@lists.ubuntu.com","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"","list_archive_url":null,"date":"2025-09-04T08:11:35","name":"[SRU,J,10/12] perf stat: Do not fail on metrics on s390 z/VM systems","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"2efdd06d4b811ecc7644d8f7639fd8cb27d8d24d","submitter":{"id":89057,"url":"http://patchwork.ozlabs.org/api/people/89057/?format=json","name":"Massimiliano Pellizzer","email":"massimiliano.pellizzer@canonical.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/ubuntu-kernel/patch/f478cf354d0d94a9716986a7699b797a065ad6a1.1756973061.git.massimiliano.pellizzer@canonical.com/mbox/","series":[{"id":472179,"url":"http://patchwork.ozlabs.org/api/series/472179/?format=json","web_url":"http://patchwork.ozlabs.org/project/ubuntu-kernel/list/?series=472179","date":"2025-09-04T08:11:25","name":"CPU-MF Counters for new IBM Z hardware - perf part (LP: #2103415)","version":1,"mbox":"http://patchwork.ozlabs.org/series/472179/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2132479/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2132479/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":"legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.ubuntu.com\n (client-ip=185.125.189.65; helo=lists.ubuntu.com;\n envelope-from=kernel-team-bounces@lists.ubuntu.com;\n receiver=patchwork.ozlabs.org)","Received":["from lists.ubuntu.com (lists.ubuntu.com [185.125.189.65])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4cHXKy63Bwz1y1S\n\tfor ; Thu, 4 Sep 2025 18:13:26 +1000 (AEST)","from localhost ([127.0.0.1] helo=lists.ubuntu.com)\n\tby lists.ubuntu.com with esmtp (Exim 4.86_2)\n\t(envelope-from )\n\tid 1uu55q-0002RF-DY; Thu, 04 Sep 2025 08:13:18 +0000","from smtp-relay-internal-1.internal ([10.131.114.114]\n helo=smtp-relay-internal-1.canonical.com)\n by lists.ubuntu.com with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.86_2) (envelope-from )\n id 1uu55c-0001hQ-75\n for kernel-team@lists.ubuntu.com; Thu, 04 Sep 2025 08:13:04 +0000","from mail-ej1-f72.google.com (mail-ej1-f72.google.com\n [209.85.218.72])\n (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest\n SHA256)\n (No client certificate requested)\n by smtp-relay-internal-1.canonical.com (Postfix) with ESMTPS id C1B033F715\n for ; Thu, 4 Sep 2025 08:13:01 +0000 (UTC)","by mail-ej1-f72.google.com with SMTP id\n a640c23a62f3a-b04827ca035so33125166b.0\n for ; Thu, 04 Sep 2025 01:13:01 -0700 (PDT)","from framework-canonical.lan\n (net-31-156-181-205.cust.vodafonedsl.it. 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'perf stat' should not fail on metrics when the referenced CPU\nCounter Measurement PMU is not available.\n\nOutput after:\n\n # perf stat -M est_cpi -- sleep 1\n\n Performance counter stats for 'sleep 1':\n\n 1,000,887,494 ns duration_time # 0.00 est_cpi\n\n 1.000887494 seconds time elapsed\n\n 0.000143000 seconds user\n 0.000662000 seconds sys\n\n #\n\nFixes: 7f76b31130680fb3 (\"perf list: Add IBM z16 event description for s390\")\nSuggested-by: Ian Rogers \nReviewed-by: Ian Rogers \nSigned-off-by: Thomas Richter \nCc: Heiko Carstens \nCc: Namhyung Kim \nCc: Sumanth Korikkar \nCc: Sven Schnelle \nCc: Vasily Gorbik \nLink: https://lore.kernel.org/r/20240404064806.1362876-2-tmricht@linux.ibm.com\nSigned-off-by: Arnaldo Carvalho de Melo \n(cherry picked from commit c2f3d7dfc7373d53286f2a5c882d3397a5070adc)\nSigned-off-by: Massimiliano Pellizzer \n---\n .../arch/s390/cf_z16/transaction.json | 28 +++++++++----------\n 1 file changed, 14 insertions(+), 14 deletions(-)","diff":"diff --git a/tools/perf/pmu-events/arch/s390/cf_z16/transaction.json b/tools/perf/pmu-events/arch/s390/cf_z16/transaction.json\nindex ec2ff78e2b5f..3ab1d3a6638c 100644\n--- a/tools/perf/pmu-events/arch/s390/cf_z16/transaction.json\n+++ b/tools/perf/pmu-events/arch/s390/cf_z16/transaction.json\n@@ -2,71 +2,71 @@\n {\n \"BriefDescription\": \"Transaction count\",\n \"MetricName\": \"transaction\",\n- \"MetricExpr\": \"TX_C_TEND + TX_NC_TEND + TX_NC_TABORT + TX_C_TABORT_SPECIAL + TX_C_TABORT_NO_SPECIAL\"\n+ \"MetricExpr\": \"TX_C_TEND + TX_NC_TEND + TX_NC_TABORT + TX_C_TABORT_SPECIAL + TX_C_TABORT_NO_SPECIAL if has_event(TX_C_TEND) else 0\"\n },\n {\n \"BriefDescription\": \"Cycles per Instruction\",\n \"MetricName\": \"cpi\",\n- \"MetricExpr\": \"CPU_CYCLES / INSTRUCTIONS\"\n+ \"MetricExpr\": \"CPU_CYCLES / INSTRUCTIONS if has_event(INSTRUCTIONS) else 0\"\n },\n {\n \"BriefDescription\": \"Problem State Instruction Ratio\",\n \"MetricName\": \"prbstate\",\n- \"MetricExpr\": \"(PROBLEM_STATE_INSTRUCTIONS / INSTRUCTIONS) * 100\"\n+ \"MetricExpr\": \"(PROBLEM_STATE_INSTRUCTIONS / INSTRUCTIONS) * 100 if has_event(INSTRUCTIONS) else 0\"\n },\n {\n \"BriefDescription\": \"Level One Miss per 100 Instructions\",\n \"MetricName\": \"l1mp\",\n- \"MetricExpr\": \"((L1I_DIR_WRITES + L1D_DIR_WRITES) / INSTRUCTIONS) * 100\"\n+ \"MetricExpr\": \"((L1I_DIR_WRITES + L1D_DIR_WRITES) / INSTRUCTIONS) * 100 if has_event(INSTRUCTIONS) else 0\"\n },\n {\n \"BriefDescription\": \"Percentage sourced from Level 2 cache\",\n \"MetricName\": \"l2p\",\n- \"MetricExpr\": \"((DCW_REQ + DCW_REQ_IV + ICW_REQ + ICW_REQ_IV) / (L1I_DIR_WRITES + L1D_DIR_WRITES)) * 100\"\n+ \"MetricExpr\": \"((DCW_REQ + DCW_REQ_IV + ICW_REQ + ICW_REQ_IV) / (L1I_DIR_WRITES + L1D_DIR_WRITES)) * 100 if has_event(DCW_REQ) else 0\"\n },\n {\n \"BriefDescription\": \"Percentage sourced from Level 3 on same chip cache\",\n \"MetricName\": \"l3p\",\n- \"MetricExpr\": \"((DCW_REQ_CHIP_HIT + DCW_ON_CHIP + DCW_ON_CHIP_IV + DCW_ON_CHIP_CHIP_HIT + ICW_REQ_CHIP_HIT + ICW_ON_CHIP + ICW_ON_CHIP_IV + ICW_ON_CHIP_CHIP_HIT) / (L1I_DIR_WRITES + L1D_DIR_WRITES)) * 100\"\n+ \"MetricExpr\": \"((DCW_REQ_CHIP_HIT + DCW_ON_CHIP + DCW_ON_CHIP_IV + DCW_ON_CHIP_CHIP_HIT + ICW_REQ_CHIP_HIT + ICW_ON_CHIP + ICW_ON_CHIP_IV + ICW_ON_CHIP_CHIP_HIT) / (L1I_DIR_WRITES + L1D_DIR_WRITES)) * 100 if has_event(DCW_REQ_CHIP_HIT) else 0\"\n },\n {\n \"BriefDescription\": \"Percentage sourced from Level 4 Local cache on same book\",\n \"MetricName\": \"l4lp\",\n- \"MetricExpr\": \"((DCW_REQ_DRAWER_HIT + DCW_ON_CHIP_DRAWER_HIT + DCW_ON_MODULE + DCW_ON_DRAWER + IDCW_ON_MODULE_IV + IDCW_ON_MODULE_CHIP_HIT + IDCW_ON_MODULE_DRAWER_HIT + IDCW_ON_DRAWER_IV + IDCW_ON_DRAWER_CHIP_HIT + IDCW_ON_DRAWER_DRAWER_HIT + ICW_REQ_DRAWER_HIT + ICW_ON_CHIP_DRAWER_HIT + ICW_ON_MODULE + ICW_ON_DRAWER) / (L1I_DIR_WRITES + L1D_DIR_WRITES)) * 100\"\n+ \"MetricExpr\": \"((DCW_REQ_DRAWER_HIT + DCW_ON_CHIP_DRAWER_HIT + DCW_ON_MODULE + DCW_ON_DRAWER + IDCW_ON_MODULE_IV + IDCW_ON_MODULE_CHIP_HIT + IDCW_ON_MODULE_DRAWER_HIT + IDCW_ON_DRAWER_IV + IDCW_ON_DRAWER_CHIP_HIT + IDCW_ON_DRAWER_DRAWER_HIT + ICW_REQ_DRAWER_HIT + ICW_ON_CHIP_DRAWER_HIT + ICW_ON_MODULE + ICW_ON_DRAWER) / (L1I_DIR_WRITES + L1D_DIR_WRITES)) * 100 if has_event(DCW_REQ_DRAWER_HIT) else 0\"\n },\n {\n \"BriefDescription\": \"Percentage sourced from Level 4 Remote cache on different book\",\n \"MetricName\": \"l4rp\",\n- \"MetricExpr\": \"((DCW_OFF_DRAWER + IDCW_OFF_DRAWER_IV + IDCW_OFF_DRAWER_CHIP_HIT + IDCW_OFF_DRAWER_DRAWER_HIT + ICW_OFF_DRAWER) / (L1I_DIR_WRITES + L1D_DIR_WRITES)) * 100\"\n+ \"MetricExpr\": \"((DCW_OFF_DRAWER + IDCW_OFF_DRAWER_IV + IDCW_OFF_DRAWER_CHIP_HIT + IDCW_OFF_DRAWER_DRAWER_HIT + ICW_OFF_DRAWER) / (L1I_DIR_WRITES + L1D_DIR_WRITES)) * 100 if has_event(DCW_OFF_DRAWER) else 0\"\n },\n {\n \"BriefDescription\": \"Percentage sourced from memory\",\n \"MetricName\": \"memp\",\n- \"MetricExpr\": \"((DCW_ON_CHIP_MEMORY + DCW_ON_MODULE_MEMORY + DCW_ON_DRAWER_MEMORY + DCW_OFF_DRAWER_MEMORY + ICW_ON_CHIP_MEMORY + ICW_ON_MODULE_MEMORY + ICW_ON_DRAWER_MEMORY + ICW_OFF_DRAWER_MEMORY) / (L1I_DIR_WRITES + L1D_DIR_WRITES)) * 100\"\n+ \"MetricExpr\": \"((DCW_ON_CHIP_MEMORY + DCW_ON_MODULE_MEMORY + DCW_ON_DRAWER_MEMORY + DCW_OFF_DRAWER_MEMORY + ICW_ON_CHIP_MEMORY + ICW_ON_MODULE_MEMORY + ICW_ON_DRAWER_MEMORY + ICW_OFF_DRAWER_MEMORY) / (L1I_DIR_WRITES + L1D_DIR_WRITES)) * 100 if has_event(DCW_ON_CHIP_MEMORY) else 0\"\n },\n {\n \"BriefDescription\": \"Cycles per Instructions from Finite cache/memory\",\n \"MetricName\": \"finite_cpi\",\n- \"MetricExpr\": \"L1C_TLB2_MISSES / INSTRUCTIONS\"\n+ \"MetricExpr\": \"L1C_TLB2_MISSES / INSTRUCTIONS if has_event(L1C_TLB2_MISSES) else 0\"\n },\n {\n \"BriefDescription\": \"Estimated Instruction Complexity CPI infinite Level 1\",\n \"MetricName\": \"est_cpi\",\n- \"MetricExpr\": \"(CPU_CYCLES / INSTRUCTIONS) - (L1C_TLB2_MISSES / INSTRUCTIONS)\"\n+ \"MetricExpr\": \"(CPU_CYCLES / INSTRUCTIONS) - (L1C_TLB2_MISSES / INSTRUCTIONS) if has_event(INSTRUCTIONS) else 0\"\n },\n {\n \"BriefDescription\": \"Estimated Sourcing Cycles per Level 1 Miss\",\n \"MetricName\": \"scpl1m\",\n- \"MetricExpr\": \"L1C_TLB2_MISSES / (L1I_DIR_WRITES + L1D_DIR_WRITES)\"\n+ \"MetricExpr\": \"L1C_TLB2_MISSES / (L1I_DIR_WRITES + L1D_DIR_WRITES) if has_event(L1C_TLB2_MISSES) else 0\"\n },\n {\n \"BriefDescription\": \"Estimated TLB CPU percentage of Total CPU\",\n \"MetricName\": \"tlb_percent\",\n- \"MetricExpr\": \"((DTLB2_MISSES + ITLB2_MISSES) / CPU_CYCLES) * (L1C_TLB2_MISSES / (L1I_PENALTY_CYCLES + L1D_PENALTY_CYCLES)) * 100\"\n+ \"MetricExpr\": \"((DTLB2_MISSES + ITLB2_MISSES) / CPU_CYCLES) * (L1C_TLB2_MISSES / (L1I_PENALTY_CYCLES + L1D_PENALTY_CYCLES)) * 100 if has_event(CPU_CYCLES) else 0\"\n },\n {\n \"BriefDescription\": \"Estimated Cycles per TLB Miss\",\n \"MetricName\": \"tlb_miss\",\n- \"MetricExpr\": \"((DTLB2_MISSES + ITLB2_MISSES) / (DTLB2_WRITES + ITLB2_WRITES)) * (L1C_TLB2_MISSES / (L1I_PENALTY_CYCLES + L1D_PENALTY_CYCLES))\"\n+ \"MetricExpr\": \"((DTLB2_MISSES + ITLB2_MISSES) / (DTLB2_WRITES + ITLB2_WRITES)) * (L1C_TLB2_MISSES / (L1I_PENALTY_CYCLES + L1D_PENALTY_CYCLES)) if has_event(DTLB2_MISSES) else 0\"\n }\n ]\n","prefixes":["SRU","J","10/12"]}