{"id":2132478,"url":"http://patchwork.ozlabs.org/api/patches/2132478/?format=json","web_url":"http://patchwork.ozlabs.org/project/ubuntu-kernel/patch/283c18ac1bfcfaa511e3c0b8910a3a46be85bb67.1756973061.git.massimiliano.pellizzer@canonical.com/","project":{"id":15,"url":"http://patchwork.ozlabs.org/api/projects/15/?format=json","name":"Ubuntu Kernel","link_name":"ubuntu-kernel","list_id":"kernel-team.lists.ubuntu.com","list_email":"kernel-team@lists.ubuntu.com","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<283c18ac1bfcfaa511e3c0b8910a3a46be85bb67.1756973061.git.massimiliano.pellizzer@canonical.com>","list_archive_url":null,"date":"2025-09-04T08:11:32","name":"[SRU,J,07/12] perf vendor events s390: Add metric for TLB and cache","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"7bb016f3cc47873162e35076cf973dfe26a68369","submitter":{"id":89057,"url":"http://patchwork.ozlabs.org/api/people/89057/?format=json","name":"Massimiliano Pellizzer","email":"massimiliano.pellizzer@canonical.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/ubuntu-kernel/patch/283c18ac1bfcfaa511e3c0b8910a3a46be85bb67.1756973061.git.massimiliano.pellizzer@canonical.com/mbox/","series":[{"id":472179,"url":"http://patchwork.ozlabs.org/api/series/472179/?format=json","web_url":"http://patchwork.ozlabs.org/project/ubuntu-kernel/list/?series=472179","date":"2025-09-04T08:11:25","name":"CPU-MF Counters for new IBM Z hardware - perf part (LP: #2103415)","version":1,"mbox":"http://patchwork.ozlabs.org/series/472179/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2132478/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2132478/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":"legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.ubuntu.com\n (client-ip=185.125.189.65; helo=lists.ubuntu.com;\n envelope-from=kernel-team-bounces@lists.ubuntu.com;\n receiver=patchwork.ozlabs.org)","Received":["from lists.ubuntu.com (lists.ubuntu.com [185.125.189.65])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4cHXKy4fJ0z1y1P\n\tfor ; Thu, 4 Sep 2025 18:13:26 +1000 (AEST)","from localhost ([127.0.0.1] helo=lists.ubuntu.com)\n\tby lists.ubuntu.com with esmtp (Exim 4.86_2)\n\t(envelope-from )\n\tid 1uu55q-0002PY-0O; Thu, 04 Sep 2025 08:13:18 +0000","from smtp-relay-internal-0.internal ([10.131.114.225]\n helo=smtp-relay-internal-0.canonical.com)\n by lists.ubuntu.com with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.86_2) (envelope-from )\n id 1uu55a-0001bv-Ff\n for kernel-team@lists.ubuntu.com; Thu, 04 Sep 2025 08:13:02 +0000","from mail-ej1-f72.google.com (mail-ej1-f72.google.com\n [209.85.218.72])\n (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest\n SHA256)\n (No client certificate requested)\n by smtp-relay-internal-0.canonical.com (Postfix) with ESMTPS id D76663F657\n for ; Thu, 4 Sep 2025 08:12:59 +0000 (UTC)","by mail-ej1-f72.google.com with SMTP id\n a640c23a62f3a-afe81959e5cso67957866b.1\n for ; Thu, 04 Sep 2025 01:12:59 -0700 (PDT)","from framework-canonical.lan\n (net-31-156-181-205.cust.vodafonedsl.it. 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"},"content":"From: Thomas Richter \n\nBugLink: https://bugs.launchpad.net/bugs/2103415\n\nAdd metrics for tlb and cache statistics:\n\n- finite_cpi: Cycles per Instructions from Finite cache/memory\n- est_cpi: Estimated Instruction Complexity CPI infinite Level 1\n- scpl1m: Estimated Sourcing Cycles per Level 1 Miss\n- tlb_percent: Estimated TLB CPU percentage of Total CPU\n- tlb_miss: Estimated Cycles per TLB Miss\n\nFor details about the formulas see this documentation:\n\n https://www.ibm.com/support/pages/system/files/inline-files/CPU%20MF%20Formulas%20including%20z16%20-%20May%202022_1.pdf\n\nOutput after:\n\n # ./perf stat -M tlb_miss -- dd if=/dev/zero of=/dev/null bs=1M count=10K\n ... dd output removed\n\n Performance counter stats for 'dd if=/dev/zero of=/dev/null bs=1M count=10K':\n\n 667,726 DTLB2_MISSES # 440.96 tlb_miss\n 198 ITLB2_WRITES\n 795,170,260 L1C_TLB2_MISSES\n 9,478 ITLB2_MISSES\n 820 DTLB2_WRITES\n 1,197,126,869 L1D_PENALTY_CYCLES\n 2,457,447 L1I_PENALTY_CYCLES\n\n 1.249342187 seconds time elapsed\n\n 0.001030000 seconds user\n 1.248105000 seconds sys\n\n #\n\nSigned-off-by: Thomas Richter \nAcked-by: Ian Rogers \nAcked-By: Sumanth Korikkar \nCc: Heiko Carstens \nCc: Sven Schnelle \nCc: Vasily Gorbik \nLink: https://lore.kernel.org/r/20230313080201.2440201-3-tmricht@linux.ibm.com\nSigned-off-by: Arnaldo Carvalho de Melo \n(cherry picked from commit 4c290d4fa3aeed74e37637acaa1a787f194fe43d)\nSigned-off-by: Massimiliano Pellizzer \n---\n .../arch/s390/cf_z13/transaction.json | 30 +++++++++++++++++++\n .../arch/s390/cf_z14/transaction.json | 25 ++++++++++++++++\n .../arch/s390/cf_z15/transaction.json | 25 ++++++++++++++++\n .../arch/s390/cf_z16/transaction.json | 25 ++++++++++++++++\n 4 files changed, 105 insertions(+)","diff":"diff --git a/tools/perf/pmu-events/arch/s390/cf_z13/transaction.json b/tools/perf/pmu-events/arch/s390/cf_z13/transaction.json\nindex 71e2c7fa734c..b941a7212a4d 100644\n--- a/tools/perf/pmu-events/arch/s390/cf_z13/transaction.json\n+++ b/tools/perf/pmu-events/arch/s390/cf_z13/transaction.json\n@@ -43,5 +43,35 @@\n \"BriefDescription\": \"Percentage sourced from memory\",\n \"MetricName\": \"memp\",\n \"MetricExpr\": \"((L1D_ONNODE_MEM_SOURCED_WRITES + L1D_ONDRAWER_MEM_SOURCED_WRITES + L1D_OFFDRAWER_MEM_SOURCED_WRITES + L1D_ONCHIP_MEM_SOURCED_WRITES + L1I_ONNODE_MEM_SOURCED_WRITES + L1I_ONDRAWER_MEM_SOURCED_WRITES + L1I_OFFDRAWER_MEM_SOURCED_WRITES + L1I_ONCHIP_MEM_SOURCED_WRITES) / (L1I_DIR_WRITES + L1D_DIR_WRITES)) * 100\"\n+ },\n+ {\n+ \"BriefDescription\": \"Cycles per Instructions from Finite cache/memory\",\n+ \"MetricName\": \"finite_cpi\",\n+ \"MetricExpr\": \"L1C_TLB1_MISSES / INSTRUCTIONS\"\n+ },\n+ {\n+ \"BriefDescription\": \"Estimated Instruction Complexity CPI infinite Level 1\",\n+ \"MetricName\": \"est_cpi\",\n+ \"MetricExpr\": \"(CPU_CYCLES / INSTRUCTIONS) - (L1C_TLB1_MISSES / INSTRUCTIONS)\"\n+ },\n+ {\n+ \"BriefDescription\": \"Estimated Sourcing Cycles per Level 1 Miss\",\n+ \"MetricName\": \"scpl1m\",\n+ \"MetricExpr\": \"L1C_TLB1_MISSES / (L1I_DIR_WRITES + L1D_DIR_WRITES)\"\n+ },\n+ {\n+ \"BriefDescription\": \"Estimated TLB CPU percentage of Total CPU\",\n+ \"MetricName\": \"tlb_percent\",\n+ \"MetricExpr\": \"((DTLB1_MISSES + ITLB1_MISSES) / CPU_CYCLES) * (L1C_TLB1_MISSES / (L1I_PENALTY_CYCLES + L1D_PENALTY_CYCLES)) * 100\"\n+ },\n+ {\n+ \"BriefDescription\": \"Estimated Cycles per TLB Miss\",\n+ \"MetricName\": \"tlb_miss\",\n+ \"MetricExpr\": \"((DTLB1_MISSES + ITLB1_MISSES) / (DTLB1_WRITES + ITLB1_WRITES)) * (L1C_TLB1_MISSES / (L1I_PENALTY_CYCLES + L1D_PENALTY_CYCLES))\"\n+ },\n+ {\n+ \"BriefDescription\": \"Page Table Entry misses\",\n+ \"MetricName\": \"pte_miss\",\n+ \"MetricExpr\": \"(TLB2_PTE_WRITES / (DTLB1_WRITES + ITLB1_WRITES)) * 100\"\n }\n ]\ndiff --git a/tools/perf/pmu-events/arch/s390/cf_z14/transaction.json b/tools/perf/pmu-events/arch/s390/cf_z14/transaction.json\nindex cca237bdb7ba..ce814ea93396 100644\n--- a/tools/perf/pmu-events/arch/s390/cf_z14/transaction.json\n+++ b/tools/perf/pmu-events/arch/s390/cf_z14/transaction.json\n@@ -43,5 +43,30 @@\n \"BriefDescription\": \"Percentage sourced from memory\",\n \"MetricName\": \"memp\",\n \"MetricExpr\": \"((L1D_ONCHIP_MEMORY_SOURCED_WRITES + L1D_ONCLUSTER_MEMORY_SOURCED_WRITES + L1D_OFFCLUSTER_MEMORY_SOURCED_WRITES + L1D_OFFDRAWER_MEMORY_SOURCED_WRITES + L1I_ONCHIP_MEMORY_SOURCED_WRITES + L1I_ONCLUSTER_MEMORY_SOURCED_WRITES + L1I_OFFCLUSTER_MEMORY_SOURCED_WRITES + L1I_OFFDRAWER_MEMORY_SOURCED_WRITES) / (L1I_DIR_WRITES + L1D_DIR_WRITES)) * 100\"\n+ },\n+ {\n+ \"BriefDescription\": \"Cycles per Instructions from Finite cache/memory\",\n+ \"MetricName\": \"finite_cpi\",\n+ \"MetricExpr\": \"L1C_TLB2_MISSES / INSTRUCTIONS\"\n+ },\n+ {\n+ \"BriefDescription\": \"Estimated Instruction Complexity CPI infinite Level 1\",\n+ \"MetricName\": \"est_cpi\",\n+ \"MetricExpr\": \"(CPU_CYCLES / INSTRUCTIONS) - (L1C_TLB2_MISSES / INSTRUCTIONS)\"\n+ },\n+ {\n+ \"BriefDescription\": \"Estimated Sourcing Cycles per Level 1 Miss\",\n+ \"MetricName\": \"scpl1m\",\n+ \"MetricExpr\": \"L1C_TLB2_MISSES / (L1I_DIR_WRITES + L1D_DIR_WRITES)\"\n+ },\n+ {\n+ \"BriefDescription\": \"Estimated TLB CPU percentage of Total CPU\",\n+ \"MetricName\": \"tlb_percent\",\n+ \"MetricExpr\": \"((DTLB2_MISSES + ITLB2_MISSES) / CPU_CYCLES) * (L1C_TLB2_MISSES / (L1I_PENALTY_CYCLES + L1D_PENALTY_CYCLES)) * 100\"\n+ },\n+ {\n+ \"BriefDescription\": \"Estimated Cycles per TLB Miss\",\n+ \"MetricName\": \"tlb_miss\",\n+ \"MetricExpr\": \"((DTLB2_MISSES + ITLB2_MISSES) / (DTLB2_WRITES + ITLB2_WRITES)) * (L1C_TLB2_MISSES / (L1I_PENALTY_CYCLES + L1D_PENALTY_CYCLES))\"\n }\n ]\ndiff --git a/tools/perf/pmu-events/arch/s390/cf_z15/transaction.json b/tools/perf/pmu-events/arch/s390/cf_z15/transaction.json\nindex cca237bdb7ba..ce814ea93396 100644\n--- a/tools/perf/pmu-events/arch/s390/cf_z15/transaction.json\n+++ b/tools/perf/pmu-events/arch/s390/cf_z15/transaction.json\n@@ -43,5 +43,30 @@\n \"BriefDescription\": \"Percentage sourced from memory\",\n \"MetricName\": \"memp\",\n \"MetricExpr\": \"((L1D_ONCHIP_MEMORY_SOURCED_WRITES + L1D_ONCLUSTER_MEMORY_SOURCED_WRITES + L1D_OFFCLUSTER_MEMORY_SOURCED_WRITES + L1D_OFFDRAWER_MEMORY_SOURCED_WRITES + L1I_ONCHIP_MEMORY_SOURCED_WRITES + L1I_ONCLUSTER_MEMORY_SOURCED_WRITES + L1I_OFFCLUSTER_MEMORY_SOURCED_WRITES + L1I_OFFDRAWER_MEMORY_SOURCED_WRITES) / (L1I_DIR_WRITES + L1D_DIR_WRITES)) * 100\"\n+ },\n+ {\n+ \"BriefDescription\": \"Cycles per Instructions from Finite cache/memory\",\n+ \"MetricName\": \"finite_cpi\",\n+ \"MetricExpr\": \"L1C_TLB2_MISSES / INSTRUCTIONS\"\n+ },\n+ {\n+ \"BriefDescription\": \"Estimated Instruction Complexity CPI infinite Level 1\",\n+ \"MetricName\": \"est_cpi\",\n+ \"MetricExpr\": \"(CPU_CYCLES / INSTRUCTIONS) - (L1C_TLB2_MISSES / INSTRUCTIONS)\"\n+ },\n+ {\n+ \"BriefDescription\": \"Estimated Sourcing Cycles per Level 1 Miss\",\n+ \"MetricName\": \"scpl1m\",\n+ \"MetricExpr\": \"L1C_TLB2_MISSES / (L1I_DIR_WRITES + L1D_DIR_WRITES)\"\n+ },\n+ {\n+ \"BriefDescription\": \"Estimated TLB CPU percentage of Total CPU\",\n+ \"MetricName\": \"tlb_percent\",\n+ \"MetricExpr\": \"((DTLB2_MISSES + ITLB2_MISSES) / CPU_CYCLES) * (L1C_TLB2_MISSES / (L1I_PENALTY_CYCLES + L1D_PENALTY_CYCLES)) * 100\"\n+ },\n+ {\n+ \"BriefDescription\": \"Estimated Cycles per TLB Miss\",\n+ \"MetricName\": \"tlb_miss\",\n+ \"MetricExpr\": \"((DTLB2_MISSES + ITLB2_MISSES) / (DTLB2_WRITES + ITLB2_WRITES)) * (L1C_TLB2_MISSES / (L1I_PENALTY_CYCLES + L1D_PENALTY_CYCLES))\"\n }\n ]\ndiff --git a/tools/perf/pmu-events/arch/s390/cf_z16/transaction.json b/tools/perf/pmu-events/arch/s390/cf_z16/transaction.json\nindex dde0735a7d22..ec2ff78e2b5f 100644\n--- a/tools/perf/pmu-events/arch/s390/cf_z16/transaction.json\n+++ b/tools/perf/pmu-events/arch/s390/cf_z16/transaction.json\n@@ -43,5 +43,30 @@\n \"BriefDescription\": \"Percentage sourced from memory\",\n \"MetricName\": \"memp\",\n \"MetricExpr\": \"((DCW_ON_CHIP_MEMORY + DCW_ON_MODULE_MEMORY + DCW_ON_DRAWER_MEMORY + DCW_OFF_DRAWER_MEMORY + ICW_ON_CHIP_MEMORY + ICW_ON_MODULE_MEMORY + ICW_ON_DRAWER_MEMORY + ICW_OFF_DRAWER_MEMORY) / (L1I_DIR_WRITES + L1D_DIR_WRITES)) * 100\"\n+ },\n+ {\n+ \"BriefDescription\": \"Cycles per Instructions from Finite cache/memory\",\n+ \"MetricName\": \"finite_cpi\",\n+ \"MetricExpr\": \"L1C_TLB2_MISSES / INSTRUCTIONS\"\n+ },\n+ {\n+ \"BriefDescription\": \"Estimated Instruction Complexity CPI infinite Level 1\",\n+ \"MetricName\": \"est_cpi\",\n+ \"MetricExpr\": \"(CPU_CYCLES / INSTRUCTIONS) - (L1C_TLB2_MISSES / INSTRUCTIONS)\"\n+ },\n+ {\n+ \"BriefDescription\": \"Estimated Sourcing Cycles per Level 1 Miss\",\n+ \"MetricName\": \"scpl1m\",\n+ \"MetricExpr\": \"L1C_TLB2_MISSES / (L1I_DIR_WRITES + L1D_DIR_WRITES)\"\n+ },\n+ {\n+ \"BriefDescription\": \"Estimated TLB CPU percentage of Total CPU\",\n+ \"MetricName\": \"tlb_percent\",\n+ \"MetricExpr\": \"((DTLB2_MISSES + ITLB2_MISSES) / CPU_CYCLES) * (L1C_TLB2_MISSES / (L1I_PENALTY_CYCLES + L1D_PENALTY_CYCLES)) * 100\"\n+ },\n+ {\n+ \"BriefDescription\": \"Estimated Cycles per TLB Miss\",\n+ \"MetricName\": \"tlb_miss\",\n+ \"MetricExpr\": \"((DTLB2_MISSES + ITLB2_MISSES) / (DTLB2_WRITES + ITLB2_WRITES)) * (L1C_TLB2_MISSES / (L1I_PENALTY_CYCLES + L1D_PENALTY_CYCLES))\"\n }\n ]\n","prefixes":["SRU","J","07/12"]}