{"id":2132474,"url":"http://patchwork.ozlabs.org/api/patches/2132474/?format=json","web_url":"http://patchwork.ozlabs.org/project/ubuntu-kernel/patch/e195ce967f9cceceff7ca09832bd94100a8937dc.1756973061.git.massimiliano.pellizzer@canonical.com/","project":{"id":15,"url":"http://patchwork.ozlabs.org/api/projects/15/?format=json","name":"Ubuntu Kernel","link_name":"ubuntu-kernel","list_id":"kernel-team.lists.ubuntu.com","list_email":"kernel-team@lists.ubuntu.com","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"","list_archive_url":null,"date":"2025-09-04T08:11:33","name":"[SRU,J,08/12] perf vendor events s390: Remove UTF-8 characters from JSON file","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"6ef9b2c1b03e743c6dd65a41df4ec7a8ffee22b5","submitter":{"id":89057,"url":"http://patchwork.ozlabs.org/api/people/89057/?format=json","name":"Massimiliano Pellizzer","email":"massimiliano.pellizzer@canonical.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/ubuntu-kernel/patch/e195ce967f9cceceff7ca09832bd94100a8937dc.1756973061.git.massimiliano.pellizzer@canonical.com/mbox/","series":[{"id":472179,"url":"http://patchwork.ozlabs.org/api/series/472179/?format=json","web_url":"http://patchwork.ozlabs.org/project/ubuntu-kernel/list/?series=472179","date":"2025-09-04T08:11:25","name":"CPU-MF Counters for new IBM Z hardware - perf part (LP: #2103415)","version":1,"mbox":"http://patchwork.ozlabs.org/series/472179/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2132474/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2132474/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":"legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.ubuntu.com\n (client-ip=185.125.189.65; helo=lists.ubuntu.com;\n envelope-from=kernel-team-bounces@lists.ubuntu.com;\n receiver=patchwork.ozlabs.org)","Received":["from lists.ubuntu.com (lists.ubuntu.com [185.125.189.65])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4cHXKq17X2z1xyS\n\tfor ; Thu, 4 Sep 2025 18:13:19 +1000 (AEST)","from localhost ([127.0.0.1] helo=lists.ubuntu.com)\n\tby lists.ubuntu.com with esmtp (Exim 4.86_2)\n\t(envelope-from )\n\tid 1uu55j-00027p-Pu; Thu, 04 Sep 2025 08:13:12 +0000","from smtp-relay-internal-1.internal ([10.131.114.114]\n helo=smtp-relay-internal-1.canonical.com)\n by lists.ubuntu.com with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.86_2) (envelope-from )\n id 1uu55b-0001hO-QN\n for kernel-team@lists.ubuntu.com; Thu, 04 Sep 2025 08:13:03 +0000","from mail-ej1-f71.google.com (mail-ej1-f71.google.com\n [209.85.218.71])\n (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest\n SHA256)\n (No client certificate requested)\n by smtp-relay-internal-1.canonical.com (Postfix) with ESMTPS id 631C83F6A9\n for ; Thu, 4 Sep 2025 08:13:01 +0000 (UTC)","by mail-ej1-f71.google.com with SMTP id\n a640c23a62f3a-afcb72a8816so57019166b.0\n for ; Thu, 04 Sep 2025 01:13:01 -0700 (PDT)","from framework-canonical.lan\n (net-31-156-181-205.cust.vodafonedsl.it. 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charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Errors-To":"kernel-team-bounces@lists.ubuntu.com","Sender":"\"kernel-team\" "},"content":"From: Thomas Richter \n\nBugLink: https://bugs.launchpad.net/bugs/2103415\n\nCommit 7f76b31130680fb3 (\"perf list: Add IBM z16 event description for\ns390\") contains the verbal description for z16 extended counter set.\n\nHowever some entries of the public description contain UTF-8 characters\nwhich breaks the build on some distros.\n\nFix this and remove the UTF-8 characters.\n\nFixes: 7f76b31130680fb3 (\"perf list: Add IBM z16 event description for s390\")\nReported-by: Arnaldo Carvalho de Melo \nSuggested-by: Heiko Carstens \nSigned-off-by: Thomas Richter \nTested-by: Arnaldo Carvalho de Melo \nCc: Sumanth Korikkar \nCc: Sven Schnelle \nCc: Thomas Richter \nCc: Vasily Gorbik \nLink: https://lore.kernel.org/r/ZBwkl77/I31AQk12@osiris\nSigned-off-by: Arnaldo Carvalho de Melo \n(cherry picked from commit eb2feb68cb7d404288493c41480843bc9f404789)\nSigned-off-by: Massimiliano Pellizzer \n---\n tools/perf/pmu-events/arch/s390/cf_z16/extended.json | 10 +++++-----\n 1 file changed, 5 insertions(+), 5 deletions(-)","diff":"diff --git a/tools/perf/pmu-events/arch/s390/cf_z16/extended.json b/tools/perf/pmu-events/arch/s390/cf_z16/extended.json\nindex c306190fc06f..c2b10ec1c6e0 100644\n--- a/tools/perf/pmu-events/arch/s390/cf_z16/extended.json\n+++ b/tools/perf/pmu-events/arch/s390/cf_z16/extended.json\n@@ -95,28 +95,28 @@\n \t\t\"EventCode\": \"145\",\n \t\t\"EventName\": \"DCW_REQ\",\n \t\t\"BriefDescription\": \"Directory Write Level 1 Data Cache from Cache\",\n-\t\t\"PublicDescription\": \"A directory write to the Level-1 Data cache directory where the returned cache line was sourced from the requestor’s Level-2 cache.\"\n+\t\t\"PublicDescription\": \"A directory write to the Level-1 Data cache directory where the returned cache line was sourced from the requestors Level-2 cache.\"\n \t},\n \t{\n \t\t\"Unit\": \"CPU-M-CF\",\n \t\t\"EventCode\": \"146\",\n \t\t\"EventName\": \"DCW_REQ_IV\",\n \t\t\"BriefDescription\": \"Directory Write Level 1 Data Cache from Cache with Intervention\",\n-\t\t\"PublicDescription\": \"A directory write to the Level-1 Data cache directory where the returned cache line was sourced from the requestor’s Level-2 cache with intervention.\"\n+\t\t\"PublicDescription\": \"A directory write to the Level-1 Data cache directory where the returned cache line was sourced from the requestors Level-2 cache with intervention.\"\n \t},\n \t{\n \t\t\"Unit\": \"CPU-M-CF\",\n \t\t\"EventCode\": \"147\",\n \t\t\"EventName\": \"DCW_REQ_CHIP_HIT\",\n \t\t\"BriefDescription\": \"Directory Write Level 1 Data Cache from Cache with Chip HP Hit\",\n-\t\t\"PublicDescription\": \"A directory write to the Level-1 Data cache directory where the returned cache line was sourced from the requestor’s Level-2 cache after using chip level horizontal persistence, Chip-HP hit.\"\n+\t\t\"PublicDescription\": \"A directory write to the Level-1 Data cache directory where the returned cache line was sourced from the requestors Level-2 cache after using chip level horizontal persistence, Chip-HP hit.\"\n \t},\n \t{\n \t\t\"Unit\": \"CPU-M-CF\",\n \t\t\"EventCode\": \"148\",\n \t\t\"EventName\": \"DCW_REQ_DRAWER_HIT\",\n \t\t\"BriefDescription\": \"Directory Write Level 1 Data Cache from Cache with Drawer HP Hit\",\n-\t\t\"PublicDescription\": \"A directory write to the Level-1 Data cache directory where the returned cache line was sourced from the requestor’s Level-2 cache after using drawer level horizontal persistence, Drawer-HP hit.\"\n+\t\t\"PublicDescription\": \"A directory write to the Level-1 Data cache directory where the returned cache line was sourced from the requestors Level-2 cache after using drawer level horizontal persistence, Drawer-HP hit.\"\n \t},\n \t{\n \t\t\"Unit\": \"CPU-M-CF\",\n@@ -284,7 +284,7 @@\n \t\t\"EventCode\": \"172\",\n \t\t\"EventName\": \"ICW_REQ_DRAWER_HIT\",\n \t\t\"BriefDescription\": \"Directory Write Level 1 Instruction Cache from Cache with Drawer HP Hit\",\n-\t\t\"PublicDescription\": \"A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from the requestor’s Level-2 cache using drawer level horizontal persistence, Drawer-HP hit.\"\n+\t\t\"PublicDescription\": \"A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from the requestors Level-2 cache using drawer level horizontal persistence, Drawer-HP hit.\"\n \t},\n \t{\n \t\t\"Unit\": \"CPU-M-CF\",\n","prefixes":["SRU","J","08/12"]}