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charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Errors-To":"kernel-team-bounces@lists.ubuntu.com","Sender":"\"kernel-team\" "},"content":"From: Thomas Richter \n\nBugLink: https://bugs.launchpad.net/bugs/2103415\n\nAdd metrics for s390 z16\n\n- Percentage sourced from Level 2 cache\n- Percentage sourced from Level 3 on same chip cache\n- Percentage sourced from Level 4 Local cache on same book\n- Percentage sourced from Level 4 Remote cache on different book\n- Percentage sourced from memory\n\nFor details about the formulas see this documentation:\nhttps://www.ibm.com/support/pages/system/files/inline-files/CPU%20MF%20Formulas%20including%20z16%20-%20May%202022_1.pdf\n\nOutput after:\n\n # ./perf stat -M l4rp -- dd if=/dev/zero of=/dev/null bs=10M count=10K\n .... dd output deleted\n\n Performance counter stats for 'dd if=/dev/zero of=/dev/null bs=10M count=10K':\n\n 0 IDCW_OFF_DRAWER_CHIP_HIT # 0.00 l4rp\n 431,866 L1I_DIR_WRITES\n 2,395 IDCW_OFF_DRAWER_IV\n 0 ICW_OFF_DRAWER\n 0 IDCW_OFF_DRAWER_DRAWER_HIT\n 1,437 DCW_OFF_DRAWER\n 425,960,793 L1D_DIR_WRITES\n\n 12.165030699 seconds time elapsed\n\n 0.001037000 seconds user\n 12.162140000 seconds sys\n #\n\nSigned-off-by: Thomas Richter \nAcked-by: Ian Rogers \nAcked-By: Sumanth Korikkar \nCc: Heiko Carstens \nCc: Sven Schnelle \nCc: Vasily Gorbik \nLink: https://lore.kernel.org/r/20230313080201.2440201-1-tmricht@linux.ibm.com\nSigned-off-by: Arnaldo Carvalho de Melo \n(cherry picked from commit f8a6cea4839bc8c76804b301dbb5522a6cacf6d5)\nSigned-off-by: Massimiliano Pellizzer \n---\n .../arch/s390/cf_z16/transaction.json | 25 +++++++++++++++++++\n 1 file changed, 25 insertions(+)","diff":"diff --git a/tools/perf/pmu-events/arch/s390/cf_z16/transaction.json b/tools/perf/pmu-events/arch/s390/cf_z16/transaction.json\nindex 86bf83b4504e..dde0735a7d22 100644\n--- a/tools/perf/pmu-events/arch/s390/cf_z16/transaction.json\n+++ b/tools/perf/pmu-events/arch/s390/cf_z16/transaction.json\n@@ -18,5 +18,30 @@\n \"BriefDescription\": \"Level One Miss per 100 Instructions\",\n \"MetricName\": \"l1mp\",\n \"MetricExpr\": \"((L1I_DIR_WRITES + L1D_DIR_WRITES) / INSTRUCTIONS) * 100\"\n+ },\n+ {\n+ \"BriefDescription\": \"Percentage sourced from Level 2 cache\",\n+ \"MetricName\": \"l2p\",\n+ \"MetricExpr\": \"((DCW_REQ + DCW_REQ_IV + ICW_REQ + ICW_REQ_IV) / (L1I_DIR_WRITES + L1D_DIR_WRITES)) * 100\"\n+ },\n+ {\n+ \"BriefDescription\": \"Percentage sourced from Level 3 on same chip cache\",\n+ \"MetricName\": \"l3p\",\n+ \"MetricExpr\": \"((DCW_REQ_CHIP_HIT + DCW_ON_CHIP + DCW_ON_CHIP_IV + DCW_ON_CHIP_CHIP_HIT + ICW_REQ_CHIP_HIT + ICW_ON_CHIP + ICW_ON_CHIP_IV + ICW_ON_CHIP_CHIP_HIT) / (L1I_DIR_WRITES + L1D_DIR_WRITES)) * 100\"\n+ },\n+ {\n+ \"BriefDescription\": \"Percentage sourced from Level 4 Local cache on same book\",\n+ \"MetricName\": \"l4lp\",\n+ \"MetricExpr\": \"((DCW_REQ_DRAWER_HIT + DCW_ON_CHIP_DRAWER_HIT + DCW_ON_MODULE + DCW_ON_DRAWER + IDCW_ON_MODULE_IV + IDCW_ON_MODULE_CHIP_HIT + IDCW_ON_MODULE_DRAWER_HIT + IDCW_ON_DRAWER_IV + IDCW_ON_DRAWER_CHIP_HIT + IDCW_ON_DRAWER_DRAWER_HIT + ICW_REQ_DRAWER_HIT + ICW_ON_CHIP_DRAWER_HIT + ICW_ON_MODULE + ICW_ON_DRAWER) / (L1I_DIR_WRITES + L1D_DIR_WRITES)) * 100\"\n+ },\n+ {\n+ \"BriefDescription\": \"Percentage sourced from Level 4 Remote cache on different book\",\n+ \"MetricName\": \"l4rp\",\n+ \"MetricExpr\": \"((DCW_OFF_DRAWER + IDCW_OFF_DRAWER_IV + IDCW_OFF_DRAWER_CHIP_HIT + IDCW_OFF_DRAWER_DRAWER_HIT + ICW_OFF_DRAWER) / (L1I_DIR_WRITES + L1D_DIR_WRITES)) * 100\"\n+ },\n+ {\n+ \"BriefDescription\": \"Percentage sourced from memory\",\n+ \"MetricName\": \"memp\",\n+ \"MetricExpr\": \"((DCW_ON_CHIP_MEMORY + DCW_ON_MODULE_MEMORY + DCW_ON_DRAWER_MEMORY + DCW_OFF_DRAWER_MEMORY + ICW_ON_CHIP_MEMORY + ICW_ON_MODULE_MEMORY + ICW_ON_DRAWER_MEMORY + ICW_OFF_DRAWER_MEMORY) / (L1I_DIR_WRITES + L1D_DIR_WRITES)) * 100\"\n }\n ]\n","prefixes":["SRU","J","06/12"]}