{"id":2070366,"url":"http://patchwork.ozlabs.org/api/patches/2070366/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20250409023711.2960618-2-maobibo@loongson.cn/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20250409023711.2960618-2-maobibo@loongson.cn>","list_archive_url":null,"date":"2025-04-09T02:36:56","name":"[v3,01/16] hw/intc/loongarch_pch: Modify name of some registers","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"e19ad733b075cce08e8ab21d025bcc5035bf394e","submitter":{"id":78914,"url":"http://patchwork.ozlabs.org/api/people/78914/?format=json","name":"Bibo Mao","email":"maobibo@loongson.cn"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20250409023711.2960618-2-maobibo@loongson.cn/mbox/","series":[{"id":451861,"url":"http://patchwork.ozlabs.org/api/series/451861/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=451861","date":"2025-04-09T02:37:00","name":"hw/intc/loongarch_pch: Cleanup with memory region ops","version":3,"mbox":"http://patchwork.ozlabs.org/series/451861/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2070366/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2070366/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":"legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)","Received":["from lists.gnu.org (lists.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4ZXRvz17Nkz1yHS\n\tfor ; Wed, 9 Apr 2025 12:38:39 +1000 (AEST)","from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from )\n\tid 1u2LJi-0006VU-PE; Tue, 08 Apr 2025 22:37:30 -0400","from eggs.gnu.org ([2001:470:142:3::10])\n by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from )\n id 1u2LJg-0006Tw-H7\n for qemu-devel@nongnu.org; Tue, 08 Apr 2025 22:37:28 -0400","from mail.loongson.cn ([114.242.206.163])\n by eggs.gnu.org with esmtp (Exim 4.90_1)\n (envelope-from ) id 1u2LJc-0007mp-O2\n for qemu-devel@nongnu.org; Tue, 08 Apr 2025 22:37:28 -0400","from loongson.cn (unknown [10.2.10.34])\n by gateway (Coremail) with SMTP id _____8BxlmlZ3fVnDq+1AA--.40119S3;\n Wed, 09 Apr 2025 10:37:13 +0800 (CST)","from localhost.localdomain (unknown [10.2.10.34])\n by front1 (Coremail) with SMTP id qMiowMBxLsdY3fVnnsR1AA--.28294S3;\n Wed, 09 Apr 2025 10:37:12 +0800 (CST)"],"From":"Bibo Mao ","To":"Song Gao ","Cc":"Jiaxun Yang ,\n\tqemu-devel@nongnu.org","Subject":"[PATCH v3 01/16] hw/intc/loongarch_pch: Modify name of some registers","Date":"Wed, 9 Apr 2025 10:36:56 +0800","Message-Id":"<20250409023711.2960618-2-maobibo@loongson.cn>","X-Mailer":"git-send-email 2.39.3","In-Reply-To":"<20250409023711.2960618-1-maobibo@loongson.cn>","References":"<20250409023711.2960618-1-maobibo@loongson.cn>","MIME-Version":"1.0","Content-Transfer-Encoding":"8bit","X-CM-TRANSID":"qMiowMBxLsdY3fVnnsR1AA--.28294S3","X-CM-SenderInfo":"xpdruxter6z05rqj20fqof0/","X-Coremail-Antispam":"1Uk129KBj93XoWxtw1ktrWrGrWxZr18AF1fAFc_yoWxXrWfpr\n yUArW2yr4DJrWxWF4xuw15ZwnrJFn7Cr9IgwsIgFyxCF1rJrykXF1DXas8GF15K3yUJr98\n Wrsxua9I93W7trbCm3ZEXasCq-sJn29KB7ZKAUJUUUU8529EdanIXcx71UUUUU7KY7ZEXa\n sCq-sGcSsGvfJ3Ic02F40EFcxC0VAKzVAqx4xG6I80ebIjqfuFe4nvWSU5nxnvy29KBjDU\n 0xBIdaVrnRJUUUyEb4IE77IF4wAFF20E14v26r1j6r4UM7CY07I20VC2zVCF04k26cxKx2\n IYs7xG6rWj6s0DM7CIcVAFz4kK6r1Y6r17M28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48v\n e4kI8wA2z4x0Y4vE2Ix0cI8IcVAFwI0_Xr0_Ar1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI\n 0_Gr0_Cr1l84ACjcxK6I8E87Iv67AKxVW0oVCq3wA2z4x0Y4vEx4A2jsIEc7CjxVAFwI0_\n GcCE3s1le2I262IYc4CY6c8Ij28IcVAaY2xG8wAqjxCEc2xF0cIa020Ex4CE44I27wAqx4\n xG64xvF2IEw4CE5I8CrVC2j2WlYx0E2Ix0cI8IcVAFwI0_Jrv_JF1lYx0Ex4A2jsIE14v2\n 6r1j6r4UMcvjeVCFs4IE7xkEbVWUJVW8JwACjcxG0xvY0x0EwIxGrwCF04k20xvY0x0EwI\n xGrwCFx2IqxVCFs4IE7xkEbVWUJVW8JwC20s026c02F40E14v26r1j6r18MI8I3I0E7480\n Y4vE14v26r106r1rMI8E67AF67kF1VAFwI0_Jrv_JF1lIxkGc2Ij64vIr41lIxAIcVC0I7\n IYx2IY67AKxVWUJVWUCwCI42IY6xIIjxv20xvEc7CjxVAFwI0_Jr0_Gr1lIxAIcVCF04k2\n 6cxKx2IYs7xG6r1j6r1xMIIF0xvEx4A2jsIE14v26r1j6r4UMIIF0xvEx4A2jsIEc7CjxV\n AFwI0_Jr0_GrUvcSsGvfC2KfnxnUUI43ZEXa7IU8zwZ7UUUUU==","Received-SPF":"pass client-ip=114.242.206.163;\n envelope-from=maobibo@loongson.cn;\n helo=mail.loongson.cn","X-Spam_score_int":"-18","X-Spam_score":"-1.9","X-Spam_bar":"-","X-Spam_report":"(-1.9 / 5.0 requ) BAYES_00=-1.9,\n RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001,\n RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001,\n SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"For some registers with width 8 bytes, its name is something like\nPCH_PIC_INT_ID_LO and PCH_PIC_INT_ID_HI. From hardware manual,\nregister name is PCH_PIC_INT_ID instead. Here name PCH_PIC_INT_ID\nis used, and PCH_PIC_INT_ID + 4 is used for PCH_PIC_INT_ID_HI.\n\nSigned-off-by: Bibo Mao \n---\n hw/intc/loongarch_pch_pic.c | 50 +++++++++++++-------------\n hw/loongarch/virt.c | 2 +-\n include/hw/intc/loongarch_pic_common.h | 27 +++++---------\n 3 files changed, 36 insertions(+), 43 deletions(-)","diff":"diff --git a/hw/intc/loongarch_pch_pic.c b/hw/intc/loongarch_pch_pic.c\nindex acd75ccb0c..2b90ccd1ff 100644\n--- a/hw/intc/loongarch_pch_pic.c\n+++ b/hw/intc/loongarch_pch_pic.c\n@@ -79,10 +79,10 @@ static uint64_t loongarch_pch_pic_low_readw(void *opaque, hwaddr addr,\n uint32_t offset = addr & 0xfff;\n \n switch (offset) {\n- case PCH_PIC_INT_ID_LO:\n+ case PCH_PIC_INT_ID:\n val = PCH_PIC_INT_ID_VAL;\n break;\n- case PCH_PIC_INT_ID_HI:\n+ case PCH_PIC_INT_ID + 4:\n /*\n * With 7A1000 manual\n * bit 0-15 pch irqchip version\n@@ -90,28 +90,29 @@ static uint64_t loongarch_pch_pic_low_readw(void *opaque, hwaddr addr,\n */\n val = deposit32(PCH_PIC_INT_ID_VER, 16, 16, s->irq_num - 1);\n break;\n- case PCH_PIC_INT_MASK_LO:\n+ case PCH_PIC_INT_MASK:\n val = (uint32_t)s->int_mask;\n break;\n- case PCH_PIC_INT_MASK_HI:\n+ case PCH_PIC_INT_MASK + 4:\n val = s->int_mask >> 32;\n break;\n- case PCH_PIC_INT_EDGE_LO:\n+ case PCH_PIC_INT_EDGE:\n val = (uint32_t)s->intedge;\n break;\n- case PCH_PIC_INT_EDGE_HI:\n+ case PCH_PIC_INT_EDGE + 4:\n val = s->intedge >> 32;\n break;\n- case PCH_PIC_HTMSI_EN_LO:\n+ case PCH_PIC_HTMSI_EN:\n val = (uint32_t)s->htmsi_en;\n break;\n- case PCH_PIC_HTMSI_EN_HI:\n+ case PCH_PIC_HTMSI_EN + 4:\n val = s->htmsi_en >> 32;\n break;\n- case PCH_PIC_AUTO_CTRL0_LO:\n- case PCH_PIC_AUTO_CTRL0_HI:\n- case PCH_PIC_AUTO_CTRL1_LO:\n- case PCH_PIC_AUTO_CTRL1_HI:\n+ case PCH_PIC_AUTO_CTRL0:\n+ case PCH_PIC_AUTO_CTRL0 + 4:\n+ case PCH_PIC_AUTO_CTRL1:\n+ case PCH_PIC_AUTO_CTRL1 + 4:\n+ /* PCH PIC connect to EXTIOI always, discard auto_ctrl access */\n break;\n default:\n break;\n@@ -140,7 +141,7 @@ static void loongarch_pch_pic_low_writew(void *opaque, hwaddr addr,\n trace_loongarch_pch_pic_low_writew(size, addr, data);\n \n switch (offset) {\n- case PCH_PIC_INT_MASK_LO:\n+ case PCH_PIC_INT_MASK:\n old = s->int_mask;\n s->int_mask = get_writew_val(old, data, 0);\n old_valid = (uint32_t)old;\n@@ -151,7 +152,7 @@ static void loongarch_pch_pic_low_writew(void *opaque, hwaddr addr,\n pch_pic_update_irq(s, (~old_valid & data), 0);\n }\n break;\n- case PCH_PIC_INT_MASK_HI:\n+ case PCH_PIC_INT_MASK + 4:\n old = s->int_mask;\n s->int_mask = get_writew_val(old, data, 1);\n old_valid = (uint32_t)(old >> 32);\n@@ -164,20 +165,20 @@ static void loongarch_pch_pic_low_writew(void *opaque, hwaddr addr,\n pch_pic_update_irq(s, int_mask << 32, 0);\n }\n break;\n- case PCH_PIC_INT_EDGE_LO:\n+ case PCH_PIC_INT_EDGE:\n s->intedge = get_writew_val(s->intedge, data, 0);\n break;\n- case PCH_PIC_INT_EDGE_HI:\n+ case PCH_PIC_INT_EDGE + 4:\n s->intedge = get_writew_val(s->intedge, data, 1);\n break;\n- case PCH_PIC_INT_CLEAR_LO:\n+ case PCH_PIC_INT_CLEAR:\n if (s->intedge & data) {\n s->intirr &= (~data);\n pch_pic_update_irq(s, data, 0);\n s->intisr &= (~data);\n }\n break;\n- case PCH_PIC_INT_CLEAR_HI:\n+ case PCH_PIC_INT_CLEAR + 4:\n value <<= 32;\n if (s->intedge & value) {\n s->intirr &= (~value);\n@@ -185,16 +186,17 @@ static void loongarch_pch_pic_low_writew(void *opaque, hwaddr addr,\n s->intisr &= (~value);\n }\n break;\n- case PCH_PIC_HTMSI_EN_LO:\n+ case PCH_PIC_HTMSI_EN:\n s->htmsi_en = get_writew_val(s->htmsi_en, data, 0);\n break;\n- case PCH_PIC_HTMSI_EN_HI:\n+ case PCH_PIC_HTMSI_EN + 4:\n s->htmsi_en = get_writew_val(s->htmsi_en, data, 1);\n break;\n- case PCH_PIC_AUTO_CTRL0_LO:\n- case PCH_PIC_AUTO_CTRL0_HI:\n- case PCH_PIC_AUTO_CTRL1_LO:\n- case PCH_PIC_AUTO_CTRL1_HI:\n+ case PCH_PIC_AUTO_CTRL0:\n+ case PCH_PIC_AUTO_CTRL0 + 4:\n+ case PCH_PIC_AUTO_CTRL1:\n+ case PCH_PIC_AUTO_CTRL1 + 4:\n+ /* discard auto_ctrl access */\n break;\n default:\n break;\ndiff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c\nindex e25864214f..8c0cc98c72 100644\n--- a/hw/loongarch/virt.c\n+++ b/hw/loongarch/virt.c\n@@ -432,7 +432,7 @@ static void virt_irq_init(LoongArchVirtMachineState *lvms)\n VIRT_IOAPIC_REG_BASE + PCH_PIC_ROUTE_ENTRY_OFFSET,\n sysbus_mmio_get_region(d, 1));\n memory_region_add_subregion(get_system_memory(),\n- VIRT_IOAPIC_REG_BASE + PCH_PIC_INT_STATUS_LO,\n+ VIRT_IOAPIC_REG_BASE + PCH_PIC_INT_STATUS,\n sysbus_mmio_get_region(d, 2));\n \n /* Connect pch_pic irqs to extioi */\ndiff --git a/include/hw/intc/loongarch_pic_common.h b/include/hw/intc/loongarch_pic_common.h\nindex 43cce48978..c04471b08d 100644\n--- a/include/hw/intc/loongarch_pic_common.h\n+++ b/include/hw/intc/loongarch_pic_common.h\n@@ -12,28 +12,19 @@\n \n #define PCH_PIC_INT_ID_VAL 0x7000000UL\n #define PCH_PIC_INT_ID_VER 0x1UL\n-#define PCH_PIC_INT_ID_LO 0x00\n-#define PCH_PIC_INT_ID_HI 0x04\n-#define PCH_PIC_INT_MASK_LO 0x20\n-#define PCH_PIC_INT_MASK_HI 0x24\n-#define PCH_PIC_HTMSI_EN_LO 0x40\n-#define PCH_PIC_HTMSI_EN_HI 0x44\n-#define PCH_PIC_INT_EDGE_LO 0x60\n-#define PCH_PIC_INT_EDGE_HI 0x64\n-#define PCH_PIC_INT_CLEAR_LO 0x80\n-#define PCH_PIC_INT_CLEAR_HI 0x84\n-#define PCH_PIC_AUTO_CTRL0_LO 0xc0\n-#define PCH_PIC_AUTO_CTRL0_HI 0xc4\n-#define PCH_PIC_AUTO_CTRL1_LO 0xe0\n-#define PCH_PIC_AUTO_CTRL1_HI 0xe4\n+#define PCH_PIC_INT_ID 0x00\n+#define PCH_PIC_INT_MASK 0x20\n+#define PCH_PIC_HTMSI_EN 0x40\n+#define PCH_PIC_INT_EDGE 0x60\n+#define PCH_PIC_INT_CLEAR 0x80\n+#define PCH_PIC_AUTO_CTRL0 0xc0\n+#define PCH_PIC_AUTO_CTRL1 0xe0\n #define PCH_PIC_ROUTE_ENTRY_OFFSET 0x100\n #define PCH_PIC_ROUTE_ENTRY_END 0x13f\n #define PCH_PIC_HTMSI_VEC_OFFSET 0x200\n #define PCH_PIC_HTMSI_VEC_END 0x23f\n-#define PCH_PIC_INT_STATUS_LO 0x3a0\n-#define PCH_PIC_INT_STATUS_HI 0x3a4\n-#define PCH_PIC_INT_POL_LO 0x3e0\n-#define PCH_PIC_INT_POL_HI 0x3e4\n+#define PCH_PIC_INT_STATUS 0x3a0\n+#define PCH_PIC_INT_POL 0x3e0\n \n #define STATUS_LO_START 0\n #define STATUS_HI_START 0x4\n","prefixes":["v3","01/16"]}