{"id":2070361,"url":"http://patchwork.ozlabs.org/api/patches/2070361/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20250409023711.2960618-5-maobibo@loongson.cn/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20250409023711.2960618-5-maobibo@loongson.cn>","list_archive_url":null,"date":"2025-04-09T02:36:59","name":"[v3,04/16] hw/intc/loongarch_pch: Set version information at initial stage","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"02648ecb413e9196081c0cd654d4fa3aef1a2c38","submitter":{"id":78914,"url":"http://patchwork.ozlabs.org/api/people/78914/?format=json","name":"Bibo Mao","email":"maobibo@loongson.cn"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20250409023711.2960618-5-maobibo@loongson.cn/mbox/","series":[{"id":451861,"url":"http://patchwork.ozlabs.org/api/series/451861/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=451861","date":"2025-04-09T02:37:00","name":"hw/intc/loongarch_pch: Cleanup with memory region ops","version":3,"mbox":"http://patchwork.ozlabs.org/series/451861/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2070361/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2070361/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":"legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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The detailed value can\nbe set at initial stage, rather than read callback.\n\nSigned-off-by: Bibo Mao \n---\n hw/intc/loongarch_pch_pic.c | 22 +++++++++++++++-------\n include/hw/intc/loongarch_pic_common.h | 17 +++++++++++++++--\n 2 files changed, 30 insertions(+), 9 deletions(-)","diff":"diff --git a/hw/intc/loongarch_pch_pic.c b/hw/intc/loongarch_pch_pic.c\nindex a2d9930ac9..ae2dbdfafe 100644\n--- a/hw/intc/loongarch_pch_pic.c\n+++ b/hw/intc/loongarch_pch_pic.c\n@@ -80,15 +80,10 @@ static uint64_t loongarch_pch_pic_low_readw(void *opaque, hwaddr addr,\n \n switch (offset) {\n case PCH_PIC_INT_ID:\n- val = PCH_PIC_INT_ID_VAL;\n+ val = s->id.data & UINT_MAX;\n break;\n case PCH_PIC_INT_ID + 4:\n- /*\n- * With 7A1000 manual\n- * bit 0-15 pch irqchip version\n- * bit 16-31 irq number supported with pch irqchip\n- */\n- val = deposit32(PCH_PIC_INT_ID_VER, 16, 16, s->irq_num - 1);\n+ val = s->id.data >> 32;\n break;\n case PCH_PIC_INT_MASK:\n val = (uint32_t)s->int_mask;\n@@ -361,6 +356,19 @@ static void loongarch_pch_pic_reset(DeviceState *d)\n LoongArchPICCommonState *s = LOONGARCH_PIC_COMMON(d);\n int i;\n \n+ /*\n+ * With Loongson 7A1000 user manual\n+ * Chapter 5.2 \"Description of Interrupt-related Registers\"\n+ *\n+ * Interrupt controller identification register 1\n+ * Bit 24-31 Interrupt Controller ID\n+ * Interrupt controller identification register 2\n+ * Bit 0-7 Interrupt Controller version number\n+ * Bit 16-23 The number of interrupt sources supported\n+ */\n+ s->id.desc.id = PCH_PIC_INT_ID_VAL;\n+ s->id.desc.version = PCH_PIC_INT_ID_VER;\n+ s->id.desc.irq_num = s->irq_num - 1;\n s->int_mask = -1;\n s->htmsi_en = 0x0;\n s->intedge = 0x0;\ndiff --git a/include/hw/intc/loongarch_pic_common.h b/include/hw/intc/loongarch_pic_common.h\nindex ef6edc15bf..fb848da4b8 100644\n--- a/include/hw/intc/loongarch_pic_common.h\n+++ b/include/hw/intc/loongarch_pic_common.h\n@@ -10,9 +10,9 @@\n #include \"hw/pci-host/ls7a.h\"\n #include \"hw/sysbus.h\"\n \n-#define PCH_PIC_INT_ID_VAL 0x7000000UL\n-#define PCH_PIC_INT_ID_VER 0x1UL\n #define PCH_PIC_INT_ID 0x00\n+#define PCH_PIC_INT_ID_VAL 0x7\n+#define PCH_PIC_INT_ID_VER 0x1\n #define PCH_PIC_INT_MASK 0x20\n #define PCH_PIC_HTMSI_EN 0x40\n #define PCH_PIC_INT_EDGE 0x60\n@@ -30,10 +30,23 @@\n OBJECT_DECLARE_TYPE(LoongArchPICCommonState,\n LoongArchPICCommonClass, LOONGARCH_PIC_COMMON)\n \n+union LoongArchPIC_ID {\n+ struct {\n+ uint64_t _reserved_0:24;\n+ uint64_t id:8;\n+ uint64_t version:8;\n+ uint64_t _reserved_1:8;\n+ uint64_t irq_num:8;\n+ uint64_t _reserved_2:8;\n+ } QEMU_PACKED desc;\n+ uint64_t data;\n+};\n+\n struct LoongArchPICCommonState {\n SysBusDevice parent_obj;\n \n qemu_irq parent_irq[64];\n+ union LoongArchPIC_ID id; /* 0x00 interrupt ID register */\n uint64_t int_mask; /* 0x020 interrupt mask register */\n uint64_t htmsi_en; /* 0x040 1=msi */\n uint64_t intedge; /* 0x060 edge=1 level=0 */\n","prefixes":["v3","04/16"]}