{"id":2000261,"url":"http://patchwork.ozlabs.org/api/patches/2000261/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/patch/e9d96144f125af640a8d88609da0e164ee89c2f1.1729577070.git.jan.kiszka@siemens.com/","project":{"id":18,"url":"http://patchwork.ozlabs.org/api/projects/18/?format=json","name":"U-Boot","link_name":"uboot","list_id":"u-boot.lists.denx.de","list_email":"u-boot@lists.denx.de","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"","list_archive_url":null,"date":"2024-10-22T06:04:21","name":"[v2,04/13] board: siemens: iot2050: Pass DDR size from FSBL","commit_ref":"10cf194e496a767684f102bd3717a2118287792c","pull_url":null,"state":"accepted","archived":false,"hash":"ae67fe7f02f976781e2009b03b958e2dc5362b79","submitter":{"id":710,"url":"http://patchwork.ozlabs.org/api/people/710/?format=json","name":"Jan Kiszka","email":"jan.kiszka@siemens.com"},"delegate":{"id":3651,"url":"http://patchwork.ozlabs.org/api/users/3651/?format=json","username":"trini","first_name":"Tom","last_name":"Rini","email":"trini@ti.com"},"mbox":"http://patchwork.ozlabs.org/project/uboot/patch/e9d96144f125af640a8d88609da0e164ee89c2f1.1729577070.git.jan.kiszka@siemens.com/mbox/","series":[{"id":429111,"url":"http://patchwork.ozlabs.org/api/series/429111/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/list/?series=429111","date":"2024-10-22T06:04:17","name":"boards: siemens: iot2050: SM variant, sysinfo support, fixes & cleanups","version":2,"mbox":"http://patchwork.ozlabs.org/series/429111/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2000261/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2000261/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n secure) header.d=siemens.com header.i=jan.kiszka@siemens.com\n header.a=rsa-sha256 header.s=fm1 header.b=bpYeBC90;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de;\n envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org)","phobos.denx.de;\n dmarc=pass (p=reject dis=none) header.from=siemens.com","phobos.denx.de;\n spf=pass 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h=Date:From:Subject:To:Message-ID:MIME-Version:Content-Type:Content-Transfer-Encoding:Cc:References:In-Reply-To;\n bh=33QB1cQ3NTSXbL0UtgY6v2lJz57vchqb9Z8WGR6j4WM=;\n b=bpYeBC90UR2CB9yFjAonxVT/76Ni5N8pTsQOqkPaAOmVSDCSJ39pz6XrHgUcbBJR3eUyhB\n KGL6Y0c56xmizzU2cryyRK/1jWGTJIU98OC4vqimn82zA9JHTj4H2enokxrhVcZx+7nYPN1j\n xJYlPg0dyt795ClQKcWe3w3vNmUdVhR6z7COy2YBVsb8XRxDw9PxmtFH2daifkQYATRL361C\n yH7V4y8XVyOeb+HX77vMjYZWkIIM3SL4/R7wAxjXMo1jolbQAaa8xoPI1Esm2s2aTofj6GNF\n xxxJUH4gdehyMWSJydBYDD5v7gWGUiogbEIybj0HI6x6nK0olKJZkRxg==;","From":"Jan Kiszka ","To":"U-Boot Mailing List ","Cc":"Bryan Brattlof ,\n\tNishanth Menon ","Subject":"[PATCH v2 04/13] board: siemens: iot2050: Pass DDR size from FSBL","Date":"Tue, 22 Oct 2024 08:04:21 +0200","Message-ID":"\n ","In-Reply-To":"","References":"","MIME-Version":"1.0","Content-Transfer-Encoding":"8bit","X-Flowmailer-Platform":"Siemens","Feedback-ID":"519:519-294854:519-21489:flowmailer","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.39","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" ","X-Virus-Scanned":"clamav-milter 0.103.8 at phobos.denx.de","X-Virus-Status":"Clean"},"content":"From: Baocheng Su \n\nDue to new DDR size introduction, the current logic of determining the\nDDR size is not able to get the correct size.\n\nInstead, the DDR size is determined by the FSBL(SEBOOT) then passed to\nu-boot through the scratchpad info.\n\nThe SEBoot version must be >= D/V01.04.01.02 to support this change.\n\nAlso now for some variants, the DDR size may > 2GB, so borrow some code\nfrom the TI evm to iot2050 to support more than 2GB DDR.\n\nSigned-off-by: Baocheng Su \nSigned-off-by: Jan Kiszka \n---\n board/siemens/iot2050/board.c | 39 ++++++++++++++++++++++++++---------\n doc/board/siemens/iot2050.rst | 3 +++\n include/configs/iot2050.h | 3 +++\n 3 files changed, 35 insertions(+), 10 deletions(-)","diff":"diff --git a/board/siemens/iot2050/board.c b/board/siemens/iot2050/board.c\nindex 85cb999f17f..16082ae2afe 100644\n--- a/board/siemens/iot2050/board.c\n+++ b/board/siemens/iot2050/board.c\n@@ -38,6 +38,8 @@ struct iot2050_info {\n \tu8 mac_addr_cnt;\n \tu8 mac_addr[8][ARP_HLEN];\n \tchar seboot_version[40 + 1];\n+\tu8 padding[3];\n+\tu32 ddr_size_mb;\n } __packed;\n \n /*\n@@ -341,25 +343,42 @@ int board_init(void)\n \n int dram_init(void)\n {\n-\tif (board_is_advanced())\n-\t\tgd->ram_size = SZ_2G;\n-\telse\n-\t\tgd->ram_size = SZ_1G;\n+\tstruct iot2050_info *info = IOT2050_INFO_DATA;\n+\tgd->ram_size = ((phys_size_t)(info->ddr_size_mb)) << 20;\n \n \treturn 0;\n }\n \n+ulong board_get_usable_ram_top(ulong total_size)\n+{\n+\t/* Limit RAM used by U-Boot to the DDR low region */\n+\tif (gd->ram_top > 0x100000000)\n+\t\treturn 0x100000000;\n+\n+\treturn gd->ram_top;\n+}\n+\n int dram_init_banksize(void)\n {\n \tdram_init();\n \n-\t/* Bank 0 declares the memory available in the DDR low region */\n-\tgd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;\n-\tgd->bd->bi_dram[0].size = gd->ram_size;\n+\tif (gd->ram_size > SZ_2G) {\n+\t\t/* Bank 0 declares the memory available in the DDR low region */\n+\t\tgd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;\n+\t\tgd->bd->bi_dram[0].size = SZ_2G;\n+\n+\t\t/* Bank 1 declares the memory available in the DDR high region */\n+\t\tgd->bd->bi_dram[1].start = CFG_SYS_SDRAM_BASE1;\n+\t\tgd->bd->bi_dram[1].size = gd->ram_size - SZ_2G;\n+\t} else {\n+\t\t/* Bank 0 declares the memory available in the DDR low region */\n+\t\tgd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;\n+\t\tgd->bd->bi_dram[0].size = gd->ram_size;\n \n-\t/* Bank 1 declares the memory available in the DDR high region */\n-\tgd->bd->bi_dram[1].start = 0;\n-\tgd->bd->bi_dram[1].size = 0;\n+\t\t/* Bank 1 declares the memory available in the DDR high region */\n+\t\tgd->bd->bi_dram[1].start = 0;\n+\t\tgd->bd->bi_dram[1].size = 0;\n+\t}\n \n \treturn 0;\n }\ndiff --git a/doc/board/siemens/iot2050.rst b/doc/board/siemens/iot2050.rst\nindex ee3c5c95846..d0c0a412097 100644\n--- a/doc/board/siemens/iot2050.rst\n+++ b/doc/board/siemens/iot2050.rst\n@@ -29,6 +29,9 @@ The following binaries from that source need to be present in the build folder:\n - seboot_pg1.bin\n - seboot_pg2.bin\n \n+Note that SE-Boot D/V01.04.01.02 or greater is required, otherwise the DDR size\n+will not be picked up correctly by U-Boot.\n+\n When using the watchdog, a related firmware for the R5 core(s) is needed, e.g.\n https://github.com/siemens/k3-rti-wdt. The name and location of the image is\n configured via CONFIG_WDT_K3_RTI_FW_FILE.\ndiff --git a/include/configs/iot2050.h b/include/configs/iot2050.h\nindex 0f92e0d25dc..5c58c7bbaab 100644\n--- a/include/configs/iot2050.h\n+++ b/include/configs/iot2050.h\n@@ -24,6 +24,9 @@\n \tfunc(USB, usb, 2)\n #endif\n \n+/* DDR Configuration */\n+#define CFG_SYS_SDRAM_BASE1\t\t0x880000000\n+\n /*\n * This defines all MMC devices, even if the basic variant has no mmc1.\n * The non-supported device will be removed from the boot targets during\n","prefixes":["v2","04/13"]}