{"id":1992928,"url":"http://patchwork.ozlabs.org/api/patches/1992928/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20241004163042.85922-26-philmd@linaro.org/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20241004163042.85922-26-philmd@linaro.org>","list_archive_url":null,"date":"2024-10-04T16:30:41","name":"[v2,25/25] hw/ppc/e500: Use explicit big-endian LD/ST API","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"623cdc5dad75fd7fe3f87668ffb92c330d16fa02","submitter":{"id":85046,"url":"http://patchwork.ozlabs.org/api/people/85046/?format=json","name":"Philippe Mathieu-Daudé","email":"philmd@linaro.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20241004163042.85922-26-philmd@linaro.org/mbox/","series":[{"id":426623,"url":"http://patchwork.ozlabs.org/api/series/426623/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=426623","date":"2024-10-04T16:30:18","name":"misc: Use explicit endian LD/ST API","version":2,"mbox":"http://patchwork.ozlabs.org/series/426623/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/1992928/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/1992928/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=adK7yN1l;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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charset=UTF-8","Content-Transfer-Encoding":"8bit","Received-SPF":"pass client-ip=2a00:1450:4864:20::12f;\n envelope-from=philmd@linaro.org; helo=mail-lf1-x12f.google.com","X-Spam_score_int":"-20","X-Spam_score":"-2.1","X-Spam_bar":"--","X-Spam_report":"(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"The 32-bit PPC architecture uses big endianness. Directly use\nthe big-endian LD/ST API for the E500 hardware.\n\nMechanical change using:\n\n $ end=be; \\\n for acc in uw w l q tul; do \\\n sed -i -e \"s/ld${acc}_p(/ld${acc}_${end}_p(/\" \\\n -e \"s/st${acc}_p(/st${acc}_${end}_p(/\" \\\n $(git grep -wlE '(ld|st)t?u?[wlq]_p' hw/*/*e500*); \\\n done\n\nSigned-off-by: Philippe Mathieu-Daudé \n---\n hw/ppc/ppce500_spin.c | 24 ++++++++++++------------\n 1 file changed, 12 insertions(+), 12 deletions(-)","diff":"diff --git a/hw/ppc/ppce500_spin.c b/hw/ppc/ppce500_spin.c\nindex e08739a443d..8e0ef9467e4 100644\n--- a/hw/ppc/ppce500_spin.c\n+++ b/hw/ppc/ppce500_spin.c\n@@ -64,9 +64,9 @@ static void spin_reset(DeviceState *dev)\n for (i = 0; i < MAX_CPUS; i++) {\n SpinInfo *info = &s->spin[i];\n \n- stl_p(&info->pir, i);\n- stq_p(&info->r3, i);\n- stq_p(&info->addr, 1);\n+ stl_be_p(&info->pir, i);\n+ stq_be_p(&info->r3, i);\n+ stq_be_p(&info->addr, 1);\n }\n }\n \n@@ -96,9 +96,9 @@ static void spin_kick(CPUState *cs, run_on_cpu_data data)\n hwaddr map_start;\n \n cpu_synchronize_state(cs);\n- stl_p(&curspin->pir, env->spr[SPR_BOOKE_PIR]);\n- env->nip = ldq_p(&curspin->addr) & (map_size - 1);\n- env->gpr[3] = ldq_p(&curspin->r3);\n+ stl_be_p(&curspin->pir, env->spr[SPR_BOOKE_PIR]);\n+ env->nip = ldq_be_p(&curspin->addr) & (map_size - 1);\n+ env->gpr[3] = ldq_be_p(&curspin->r3);\n env->gpr[4] = 0;\n env->gpr[5] = 0;\n env->gpr[6] = 0;\n@@ -106,7 +106,7 @@ static void spin_kick(CPUState *cs, run_on_cpu_data data)\n env->gpr[8] = 0;\n env->gpr[9] = 0;\n \n- map_start = ldq_p(&curspin->addr) & ~(map_size - 1);\n+ map_start = ldq_be_p(&curspin->addr) & ~(map_size - 1);\n mmubooke_create_initial_mapping(env, 0, map_start, map_size);\n \n cs->halted = 0;\n@@ -141,14 +141,14 @@ static void spin_write(void *opaque, hwaddr addr, uint64_t value,\n stb_p(curspin_p, value);\n break;\n case 2:\n- stw_p(curspin_p, value);\n+ stw_be_p(curspin_p, value);\n break;\n case 4:\n- stl_p(curspin_p, value);\n+ stl_be_p(curspin_p, value);\n break;\n }\n \n- if (!(ldq_p(&curspin->addr) & 1)) {\n+ if (!(ldq_be_p(&curspin->addr) & 1)) {\n /* run CPU */\n run_on_cpu(cpu, spin_kick, RUN_ON_CPU_HOST_PTR(curspin));\n }\n@@ -163,9 +163,9 @@ static uint64_t spin_read(void *opaque, hwaddr addr, unsigned len)\n case 1:\n return ldub_p(spin_p);\n case 2:\n- return lduw_p(spin_p);\n+ return lduw_be_p(spin_p);\n case 4:\n- return ldl_p(spin_p);\n+ return ldl_be_p(spin_p);\n default:\n hw_error(\"ppce500: unexpected %s with len = %u\", __func__, len);\n }\n","prefixes":["v2","25/25"]}