{"id":1992912,"url":"http://patchwork.ozlabs.org/api/patches/1992912/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20241004163042.85922-24-philmd@linaro.org/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20241004163042.85922-24-philmd@linaro.org>","list_archive_url":null,"date":"2024-10-04T16:30:39","name":"[v2,23/25] target/s390x: Use explicit big-endian LD/ST API","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"8dfb3500aa2c21635406ba88db14cf7aeabba934","submitter":{"id":85046,"url":"http://patchwork.ozlabs.org/api/people/85046/?format=json","name":"Philippe Mathieu-Daudé","email":"philmd@linaro.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20241004163042.85922-24-philmd@linaro.org/mbox/","series":[{"id":426623,"url":"http://patchwork.ozlabs.org/api/series/426623/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=426623","date":"2024-10-04T16:30:18","name":"misc: Use explicit endian LD/ST API","version":2,"mbox":"http://patchwork.ozlabs.org/series/426623/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/1992912/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/1992912/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=pU3hSHe8;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from lists.gnu.org (lists.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4XKvS71XHLz1xt7\n\tfor ; Sat, 5 Oct 2024 02:40:55 +1000 (AEST)","from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from )\n\tid 1swlJ9-0004gS-HQ; Fri, 04 Oct 2024 12:37:35 -0400","from eggs.gnu.org ([2001:470:142:3::10])\n by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from ) id 1swlIE-0001p2-HA\n for qemu-devel@nongnu.org; Fri, 04 Oct 2024 12:36:40 -0400","from mail-lj1-x22f.google.com ([2a00:1450:4864:20::22f])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from ) id 1swlI8-0006fr-Ho\n for qemu-devel@nongnu.org; Fri, 04 Oct 2024 12:36:36 -0400","by mail-lj1-x22f.google.com with SMTP id\n 38308e7fff4ca-2fac6b3c220so34773751fa.2\n for ; Fri, 04 Oct 2024 09:36:30 -0700 (PDT)","from localhost.localdomain ([91.223.100.150])\n by smtp.gmail.com with ESMTPSA id\n 38308e7fff4ca-2faf9ac4415sm210841fa.34.2024.10.04.09.36.22\n (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256);\n Fri, 04 Oct 2024 09:36:26 -0700 (PDT)"],"DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=linaro.org; s=google; t=1728059788; x=1728664588; darn=nongnu.org;\n h=content-transfer-encoding:mime-version:references:in-reply-to\n :message-id:date:subject:cc:to:from:from:to:cc:subject:date\n :message-id:reply-to;\n bh=NkIrQblPdREZDLEsszsFCn2NBix9iyMsfxXdICSQWJM=;\n b=pU3hSHe8xnDOmzLEEnVMOeqmlNZu5cvpqCCCzAIYx/+ZufvQuam50aPZhDWuLLVP33\n Stk21TgLBxz4vTM6lc3yZ50trFiWFqHl0939T8ZuUefKEDc6XkHQffnynuN1HRts9wPa\n hVinW0Y/jPQQi4rmEqNDRjtneo5yfoSq9H2EZL7bWelTb+uWxUgDxKWvMmOiXe5wIFrP\n GjzI6MJSJkZbDTW/DxEKBqpIjhOKcskaNlv7Uz1HTC9VJuTtQyK/MC7PNqa/lTxRaoJt\n ZLocksa57hTbJ9xl22NEmm58T7JR2+zNnv2qwGhuT4xPlXzgAiLgnUWT8SEyDmri8Q3C\n 2APA==","X-Google-DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=1e100.net; s=20230601; t=1728059789; x=1728664589;\n h=content-transfer-encoding:mime-version:references:in-reply-to\n :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc\n :subject:date:message-id:reply-to;\n bh=NkIrQblPdREZDLEsszsFCn2NBix9iyMsfxXdICSQWJM=;\n b=CkB9VobOzpldW+QXjyl8MSRwHj5KltA0PBeWvC8rPNBu2sQDtgWa0LARAXeIuI5ENm\n 8PjSPKbQe2dotkdt2XMdCLvtalcgh0UzNg+6HrSJKBYmsOlh22R0aam8rxM4dcj6Z2/M\n AyQ+GD+yKT92T4f9RBgNTqlnzseidugMqd0fWGdyrphoy/kyH0NDuCPnGnNUN3ERB9FW\n bhR86n49E44EjIaIOQ9KenU8JIP1WdUROGhWeVAINY46wDWyiKkRWjJoSU6DdvVAnKM5\n z9AD86lZ05gfVcax2oqwJjX0cL98r5xNXNxkt+QaBdPoIuVFwOjdKYOTe3HKIO3MbKai\n 3qHA==","X-Gm-Message-State":"AOJu0Yxlh/KJLOoWBmNiBPlCzOeORz3Udromz80JTNmxsKUmRFoq2fpl\n efF4B/Sg/qUkSPB6NfH9KQQqMAn57z4408fIFnepNOqZ05P6QuEc4Tza/o/ZdQT/bIj753njIsJ\n 8XBdugg==","X-Google-Smtp-Source":"\n AGHT+IFXe3VmMv5EzunM2JXMxyDiLVkssr/VTcquycpTrBjrxYevQ0JVM6YBDEfYkhyEpIO0rZPlKw==","X-Received":"by 2002:a05:651c:b0b:b0:2fa:f5f9:4194 with SMTP id\n 38308e7fff4ca-2faf5f94416mr23634551fa.27.1728059788500;\n Fri, 04 Oct 2024 09:36:28 -0700 (PDT)","From":"=?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= ","To":"qemu-devel@nongnu.org","Cc":"qemu-riscv@nongnu.org, qemu-s390x@nongnu.org,\n Thomas Huth ,\n Richard Henderson ,\n Pierrick Bouvier , qemu-ppc@nongnu.org,\n\t=?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= ","Subject":"[PATCH v2 23/25] target/s390x: Use explicit big-endian LD/ST API","Date":"Fri, 4 Oct 2024 13:30:39 -0300","Message-ID":"<20241004163042.85922-24-philmd@linaro.org>","X-Mailer":"git-send-email 2.45.2","In-Reply-To":"<20241004163042.85922-1-philmd@linaro.org>","References":"<20241004163042.85922-1-philmd@linaro.org>","MIME-Version":"1.0","Content-Type":"text/plain; charset=UTF-8","Content-Transfer-Encoding":"8bit","Received-SPF":"pass client-ip=2a00:1450:4864:20::22f;\n envelope-from=philmd@linaro.org; helo=mail-lj1-x22f.google.com","X-Spam_score_int":"-20","X-Spam_score":"-2.1","X-Spam_bar":"--","X-Spam_report":"(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"The S390X architecture uses big endianness. Directly use\nthe big-endian LD/ST API.\n\nMechanical change using:\n\n $ end=be; \\\n for acc in uw w l q tul; do \\\n sed -i -e \"s/ld${acc}_p(/ld${acc}_${end}_p(/\" \\\n -e \"s/st${acc}_p(/st${acc}_${end}_p(/\" \\\n $(git grep -wlE '(ld|st)t?u?[wlq]_p' target/s390x/); \\\n done\n\nSigned-off-by: Philippe Mathieu-Daudé \n---\n target/s390x/gdbstub.c | 34 +++++++++++++++++-----------------\n target/s390x/ioinst.c | 2 +-\n 2 files changed, 18 insertions(+), 18 deletions(-)","diff":"diff --git a/target/s390x/gdbstub.c b/target/s390x/gdbstub.c\nindex 9ffec0bccbc..63373f02cef 100644\n--- a/target/s390x/gdbstub.c\n+++ b/target/s390x/gdbstub.c\n@@ -46,7 +46,7 @@ int s390_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)\n int s390_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)\n {\n CPUS390XState *env = cpu_env(cs);\n- target_ulong tmpl = ldq_p(mem_buf);\n+ target_ulong tmpl = ldq_be_p(mem_buf);\n \n switch (n) {\n case S390_PSWM_REGNUM:\n@@ -88,7 +88,7 @@ static int cpu_write_ac_reg(CPUState *cs, uint8_t *mem_buf, int n)\n \n switch (n) {\n case S390_A0_REGNUM ... S390_A15_REGNUM:\n- env->aregs[n] = ldl_p(mem_buf);\n+ env->aregs[n] = ldl_be_p(mem_buf);\n cpu_synchronize_post_init(env_cpu(env));\n return 4;\n default:\n@@ -123,10 +123,10 @@ static int cpu_write_fp_reg(CPUState *cs, uint8_t *mem_buf, int n)\n \n switch (n) {\n case S390_FPC_REGNUM:\n- env->fpc = ldl_p(mem_buf);\n+ env->fpc = ldl_be_p(mem_buf);\n return 4;\n case S390_F0_REGNUM ... S390_F15_REGNUM:\n- *get_freg(env, n - S390_F0_REGNUM) = ldq_p(mem_buf);\n+ *get_freg(env, n - S390_F0_REGNUM) = ldq_be_p(mem_buf);\n return 8;\n default:\n return 0;\n@@ -167,11 +167,11 @@ static int cpu_write_vreg(CPUState *cs, uint8_t *mem_buf, int n)\n \n switch (n) {\n case S390_V0L_REGNUM ... S390_V15L_REGNUM:\n- env->vregs[n][1] = ldq_p(mem_buf + 8);\n+ env->vregs[n][1] = ldq_be_p(mem_buf + 8);\n return 8;\n case S390_V16_REGNUM ... S390_V31_REGNUM:\n- env->vregs[n][0] = ldq_p(mem_buf);\n- env->vregs[n][1] = ldq_p(mem_buf + 8);\n+ env->vregs[n][0] = ldq_be_p(mem_buf);\n+ env->vregs[n][1] = ldq_be_p(mem_buf + 8);\n return 16;\n default:\n return 0;\n@@ -203,7 +203,7 @@ static int cpu_write_c_reg(CPUState *cs, uint8_t *mem_buf, int n)\n \n switch (n) {\n case S390_C0_REGNUM ... S390_C15_REGNUM:\n- env->cregs[n] = ldq_p(mem_buf);\n+ env->cregs[n] = ldq_be_p(mem_buf);\n if (tcg_enabled()) {\n tlb_flush(env_cpu(env));\n }\n@@ -246,19 +246,19 @@ static int cpu_write_virt_reg(CPUState *cs, uint8_t *mem_buf, int n)\n \n switch (n) {\n case S390_VIRT_CKC_REGNUM:\n- env->ckc = ldq_p(mem_buf);\n+ env->ckc = ldq_be_p(mem_buf);\n cpu_synchronize_post_init(cs);\n return 8;\n case S390_VIRT_CPUTM_REGNUM:\n- env->cputm = ldq_p(mem_buf);\n+ env->cputm = ldq_be_p(mem_buf);\n cpu_synchronize_post_init(cs);\n return 8;\n case S390_VIRT_BEA_REGNUM:\n- env->gbea = ldq_p(mem_buf);\n+ env->gbea = ldq_be_p(mem_buf);\n cpu_synchronize_post_init(cs);\n return 8;\n case S390_VIRT_PREFIX_REGNUM:\n- env->psa = ldq_p(mem_buf);\n+ env->psa = ldq_be_p(mem_buf);\n cpu_synchronize_post_init(cs);\n return 8;\n default:\n@@ -298,19 +298,19 @@ static int cpu_write_virt_kvm_reg(CPUState *cs, uint8_t *mem_buf, int n)\n \n switch (n) {\n case S390_VIRT_KVM_PP_REGNUM:\n- env->pp = ldq_p(mem_buf);\n+ env->pp = ldq_be_p(mem_buf);\n cpu_synchronize_post_init(env_cpu(env));\n return 8;\n case S390_VIRT_KVM_PFT_REGNUM:\n- env->pfault_token = ldq_p(mem_buf);\n+ env->pfault_token = ldq_be_p(mem_buf);\n cpu_synchronize_post_init(env_cpu(env));\n return 8;\n case S390_VIRT_KVM_PFS_REGNUM:\n- env->pfault_select = ldq_p(mem_buf);\n+ env->pfault_select = ldq_be_p(mem_buf);\n cpu_synchronize_post_init(env_cpu(env));\n return 8;\n case S390_VIRT_KVM_PFC_REGNUM:\n- env->pfault_compare = ldq_p(mem_buf);\n+ env->pfault_compare = ldq_be_p(mem_buf);\n cpu_synchronize_post_init(env_cpu(env));\n return 8;\n default:\n@@ -338,7 +338,7 @@ static int cpu_write_gs_reg(CPUState *cs, uint8_t *mem_buf, int n)\n S390CPU *cpu = S390_CPU(cs);\n CPUS390XState *env = &cpu->env;\n \n- env->gscb[n] = ldq_p(mem_buf);\n+ env->gscb[n] = ldq_be_p(mem_buf);\n cpu_synchronize_post_init(env_cpu(env));\n return 8;\n }\ndiff --git a/target/s390x/ioinst.c b/target/s390x/ioinst.c\nindex bbe45a497a8..a944f16c254 100644\n--- a/target/s390x/ioinst.c\n+++ b/target/s390x/ioinst.c\n@@ -603,7 +603,7 @@ static int chsc_sei_nt2_have_event(void)\n #define CHSC_SEI_NT2 (1ULL << 61)\n static void ioinst_handle_chsc_sei(ChscReq *req, ChscResp *res)\n {\n- uint64_t selection_mask = ldq_p(&req->param1);\n+ uint64_t selection_mask = ldq_be_p(&req->param1);\n uint8_t *res_flags = (uint8_t *)res->data;\n int have_event = 0;\n int have_more = 0;\n","prefixes":["v2","23/25"]}