{"id":1936166,"url":"http://patchwork.ozlabs.org/api/patches/1936166/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-aspeed/patch/20240516181907.3468796-25-eajames@linux.ibm.com/","project":{"id":57,"url":"http://patchwork.ozlabs.org/api/projects/57/?format=json","name":"Linux ASPEED SoC development","link_name":"linux-aspeed","list_id":"linux-aspeed.lists.ozlabs.org","list_email":"linux-aspeed@lists.ozlabs.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20240516181907.3468796-25-eajames@linux.ibm.com>","list_archive_url":null,"date":"2024-05-16T18:18:51","name":"[v3,24/40] fsi: aspeed: Add interrupt support","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"9e78cba382aa4d671002245100f92ac3f197f18c","submitter":{"id":74989,"url":"http://patchwork.ozlabs.org/api/people/74989/?format=json","name":"Eddie James","email":"eajames@linux.ibm.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/linux-aspeed/patch/20240516181907.3468796-25-eajames@linux.ibm.com/mbox/","series":[{"id":407101,"url":"http://patchwork.ozlabs.org/api/series/407101/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-aspeed/list/?series=407101","date":"2024-05-16T18:18:31","name":"fsi: Add interrupt support","version":3,"mbox":"http://patchwork.ozlabs.org/series/407101/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/1936166/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/1936166/checks/","tags":{},"related":[],"headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-aspeed@lists.ozlabs.org"],"Delivered-To":["patchwork-incoming@legolas.ozlabs.org","linux-aspeed@lists.ozlabs.org"],"Authentication-Results":["legolas.ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n unprotected) header.d=ibm.com header.i=@ibm.com header.a=rsa-sha256\n header.s=pp1 header.b=d/OCKQ50;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.ozlabs.org\n (client-ip=2404:9400:2:0:216:3eff:fee1:b9f1; helo=lists.ozlabs.org;\n envelope-from=linux-aspeed-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org;\n receiver=patchwork.ozlabs.org)","lists.ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n unprotected) header.d=ibm.com header.i=@ibm.com header.a=rsa-sha256\n header.s=pp1 header.b=d/OCKQ50;\n\tdkim-atps=neutral","lists.ozlabs.org;\n dmarc=pass (p=none dis=none) header.from=linux.ibm.com","lists.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=ibm.com header.i=@ibm.com header.a=rsa-sha256\n header.s=pp1 header.b=d/OCKQ50;\n\tdkim-atps=neutral","lists.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=linux.ibm.com\n (client-ip=148.163.158.5; helo=mx0b-001b2d01.pphosted.com;\n envelope-from=eajames@linux.ibm.com; receiver=lists.ozlabs.org)"],"Received":["from lists.ozlabs.org (lists.ozlabs.org\n [IPv6:2404:9400:2:0:216:3eff:fee1:b9f1])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange X25519 server-signature ECDSA (secp384r1))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4VgJMr581hz1yfq\n\tfor ; Fri, 17 May 2024 04:22:00 +1000 (AEST)","from boromir.ozlabs.org (localhost [IPv6:::1])\n\tby lists.ozlabs.org (Postfix) with ESMTP id 4VgJMr2x2Qz3fpd\n\tfor ; Fri, 17 May 2024 04:22:00 +1000 (AEST)","from mx0b-001b2d01.pphosted.com (mx0b-001b2d01.pphosted.com\n [148.163.158.5])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby lists.ozlabs.org (Postfix) with ESMTPS id 4VgJK708lJz3ftV;\n\tFri, 17 May 2024 04:19:38 +1000 (AEST)","from pps.filterd (m0353725.ppops.net [127.0.0.1])\n\tby mx0a-001b2d01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id\n 44GEwfd5032739;\n\tThu, 16 May 2024 18:19:20 GMT","from ppma12.dal12v.mail.ibm.com\n (dc.9e.1632.ip4.static.sl-reverse.com [50.22.158.220])\n\tby mx0a-001b2d01.pphosted.com (PPS) with ESMTPS id 3y5mce8frt-1\n\t(version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT);\n\tThu, 16 May 2024 18:19:20 +0000","from pps.filterd (ppma12.dal12v.mail.ibm.com [127.0.0.1])\n\tby ppma12.dal12v.mail.ibm.com (8.17.1.19/8.17.1.19) with ESMTP id\n 44GGHsWJ018810;\n\tThu, 16 May 2024 18:19:19 GMT","from smtprelay07.wdc07v.mail.ibm.com ([172.16.1.74])\n\tby ppma12.dal12v.mail.ibm.com (PPS) with ESMTPS id 3y2k0tuqef-1\n\t(version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT);\n\tThu, 16 May 2024 18:19:19 +0000","from smtpav05.dal12v.mail.ibm.com (smtpav05.dal12v.mail.ibm.com\n [10.241.53.104])\n\tby smtprelay07.wdc07v.mail.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id\n 44GIJGCY27787942\n\t(version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK);\n\tThu, 16 May 2024 18:19:18 GMT","from smtpav05.dal12v.mail.ibm.com (unknown [127.0.0.1])\n\tby IMSVA (Postfix) with ESMTP id C114B5807C;\n\tThu, 16 May 2024 18:19:14 +0000 (GMT)","from smtpav05.dal12v.mail.ibm.com (unknown [127.0.0.1])\n\tby IMSVA (Postfix) with ESMTP id 8350558076;\n\tThu, 16 May 2024 18:19:14 +0000 (GMT)","from slate16.aus.stglabs.ibm.com (unknown [9.61.107.19])\n\tby smtpav05.dal12v.mail.ibm.com (Postfix) with ESMTP;\n\tThu, 16 May 2024 18:19:14 +0000 (GMT)"],"DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed; d=ibm.com;\n h=from : to : cc : subject\n : date : message-id : in-reply-to : references : mime-version :\n content-transfer-encoding; s=pp1;\n bh=8PJMQwkXBuHRk4+y67UGNnhw/k8TP4I96ElVzPKL2DE=;\n b=d/OCKQ50Fxj5glIyNRwMuFydF2wiMZcO81DgAf8NxMV0us75gYvP8nnvfAvcWJw8JTZX\n U+W4l6I76GUSiQ6dXieV3s5QPi0tEUd/GDTpX8mZKSNcF4WnVLkq9xhKIhbkTZDEjlnY\n IREX7iA6HRGPFzPQXRjOn/tTu0ZUKhWfuqNQt+5uWg2Gd1+vvxMDqGJsU/b6IWpHxDfW\n YhgQm6bMAZZNAsWMdplw3QvHF0i6msT3Sbu+opy80CJeRmIlxdfuZdcXq7QRG5aRmzyp\n w6vRKi85KzP7+meY44HQBIzuyTcp6zlGZmbppu5n4qJk0sIa50KAMSMIebRO8yzICgCr uQ==","From":"Eddie James ","To":"linux-fsi@lists.ozlabs.org","Subject":"[PATCH v3 24/40] fsi: aspeed: Add interrupt support","Date":"Thu, 16 May 2024 13:18:51 -0500","Message-Id":"<20240516181907.3468796-25-eajames@linux.ibm.com>","X-Mailer":"git-send-email 2.39.3","In-Reply-To":"<20240516181907.3468796-1-eajames@linux.ibm.com>","References":"<20240516181907.3468796-1-eajames@linux.ibm.com>","MIME-Version":"1.0","Content-Transfer-Encoding":"8bit","X-TM-AS-GCONF":"00","X-Proofpoint-GUID":"5r-YgToBKnwZojzrSD1vNtqMHpp0PV0F","X-Proofpoint-ORIG-GUID":"5r-YgToBKnwZojzrSD1vNtqMHpp0PV0F","X-Proofpoint-Virus-Version":"vendor=baseguard\n engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.650,FMLib:17.11.176.26\n definitions=2024-05-16_07,2024-05-15_01,2023-05-22_02","X-Proofpoint-Spam-Details":"rule=outbound_notspam policy=outbound score=0\n mlxlogscore=889 phishscore=0\n adultscore=0 priorityscore=1501 malwarescore=0 suspectscore=0 bulkscore=0\n mlxscore=0 spamscore=0 lowpriorityscore=0 impostorscore=0 clxscore=1015\n classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2405010000\n definitions=main-2405160132","X-BeenThere":"linux-aspeed@lists.ozlabs.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"Linux ASPEED SoC development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Cc":"andi.shyti@kernel.org, linux-aspeed@lists.ozlabs.org, jk@ozlabs.org,\n alistair@popple.id.au, linux-kernel@vger.kernel.org,\n linux-spi@vger.kernel.org, broonie@kernel.org, andrew@codeconstruct.com.au,\n linux-i2c@vger.kernel.org","Errors-To":"linux-aspeed-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org","Sender":"\"Linux-aspeed\"\n "},"content":"Handle slave interrupts and pass them to the FSI core.\n\nSigned-off-by: Eddie James \n---\n drivers/fsi/fsi-master-aspeed.c | 106 ++++++++++++++++++++++-\n include/trace/events/fsi_master_aspeed.h | 12 +++\n 2 files changed, 115 insertions(+), 3 deletions(-)","diff":"diff --git a/drivers/fsi/fsi-master-aspeed.c b/drivers/fsi/fsi-master-aspeed.c\nindex eecd64bc29512..34f4c9e00e43d 100644\n--- a/drivers/fsi/fsi-master-aspeed.c\n+++ b/drivers/fsi/fsi-master-aspeed.c\n@@ -6,6 +6,8 @@\n #include \n #include \n #include \n+#include \n+#include \n #include \n #include \n #include \n@@ -25,11 +27,13 @@ struct fsi_master_aspeed_data {\n struct fsi_master_aspeed {\n \tstruct fsi_master\tmaster;\n \tspinlock_t\t\tlock;\t/* protect HW access */\n+\tstruct irq_domain\t*irq_domain;\n \tstruct device\t\t*dev;\n \tvoid __iomem\t\t*base;\n \tvoid __iomem\t\t*ctrl;\n \tstruct clk\t\t*clk;\n \tstruct gpio_desc\t*cfam_reset_gpio;\n+\tu32\t\t\tirq_mask;\n };\n \n #define to_fsi_master_aspeed(m) \\\n@@ -79,6 +83,11 @@ static const u32 fsi_base = 0xa0000000;\n #define STATUS_TIMEOUT\t\tBIT(4)\n \n /* OPB_IRQ_MASK */\n+#define FSI_MASTER_ERROR_IRQ\tBIT(28)\n+#define FSI_PORT_ERROR_IRQ\tBIT(27)\n+#define FSI_HOTPLUG_IRQ\t\tBIT(26)\n+#define FSI_REMOTE_SLV_IRQ(l)\t(BIT(FSI_REMOTE_SLV_IRQ_BIT) << (l))\n+#define FSI_REMOTE_SLV_IRQ_BIT\t18\n #define OPB1_XFER_ACK_EN BIT(17)\n #define OPB0_XFER_ACK_EN BIT(16)\n \n@@ -96,7 +105,7 @@ static const u32 fsi_base = 0xa0000000;\n #define OPB_RC_CTRL_OPB\t\tBIT(18)\t/* Access controller over OPB, not AHB (AST27xx+) */\n #define OPB_RC_XFER_ACK_EN\tBIT(16)\t/* Enable OPBx xfer ack bit without mask */\n #define OPB_RC_COUNT\t\tGENMASK(15, 0)\t/* Number of retries */\n-#define OPB_RC_DEFAULT\t\t0x10\n+#define OPB_RC_DEFAULT\t\t(OPB_RC_XFER_ACK_EN | 0x10)\n \n #define CREATE_TRACE_POINTS\n #include \n@@ -322,11 +331,76 @@ static int aspeed_master_break(struct fsi_master *master, int link)\n \treturn aspeed_master_write(master, link, 0, addr, &cmd, 4);\n }\n \n+static int aspeed_master_link_enable(struct fsi_master *master, int link, bool enable)\n+{\n+\tstruct fsi_master_aspeed *aspeed = to_fsi_master_aspeed(master);\n+\tunsigned long flags;\n+\tint rc;\n+\n+\tspin_lock_irqsave(&aspeed->lock, flags);\n+\tif (enable) {\n+\t\trc = fsi_master_link_enable(master, link, enable);\n+\t\tif (rc)\n+\t\t\tgoto done;\n+\n+\t\taspeed->irq_mask |= FSI_REMOTE_SLV_IRQ(link);\n+\t\twritel(aspeed->irq_mask, aspeed->base + OPB_IRQ_MASK);\n+\t} else {\n+\t\taspeed->irq_mask &= ~FSI_REMOTE_SLV_IRQ(link);\n+\t\twritel(aspeed->irq_mask, aspeed->base + OPB_IRQ_MASK);\n+\n+\t\trc = fsi_master_link_enable(master, link, enable);\n+\t}\n+\n+done:\n+\tspin_unlock_irqrestore(&aspeed->lock, flags);\n+\treturn rc;\n+}\n+\n+static irqreturn_t aspeed_master_irq(int irq, void *data)\n+{\n+\tstruct fsi_master_aspeed *aspeed = data;\n+\tunsigned long size = FSI_REMOTE_SLV_IRQ_BIT + aspeed->master.n_links;\n+\tunsigned long bit = FSI_REMOTE_SLV_IRQ_BIT;\n+\tunsigned long status;\n+\n+\tstatus = readl(aspeed->base + OPB_IRQ_STATUS);\n+\twritel(0, aspeed->base + OPB_IRQ_MASK);\n+\n+\tfor_each_set_bit_from(bit, &status, size)\n+\t\tfsi_master_irq(&aspeed->master, aspeed->irq_domain, bit - FSI_REMOTE_SLV_IRQ_BIT);\n+\n+\twritel(status, aspeed->base + OPB_IRQ_STATUS);\n+\twritel(0, aspeed->base + OPB_IRQ_STATUS);\n+\twritel(aspeed->irq_mask, aspeed->base + OPB_IRQ_MASK);\n+\n+\ttrace_fsi_master_aspeed_irq(status);\n+\treturn IRQ_HANDLED;\n+}\n+\n+static int aspeed_master_irqd_map(struct irq_domain *domain, unsigned int irq,\n+\t\t\t\t irq_hw_number_t hwirq)\n+{\n+\tstruct fsi_master_aspeed *aspeed = domain->host_data;\n+\n+\tirq_set_chip_and_handler(irq, &aspeed->master.irq_chip, handle_simple_irq);\n+\tirq_set_chip_data(irq, &aspeed->master);\n+\n+\treturn 0;\n+}\n+\n+static const struct irq_domain_ops aspeed_master_irq_domain_ops = {\n+\t.map = aspeed_master_irqd_map,\n+};\n+\n static void aspeed_master_release(struct device *dev)\n {\n \tstruct fsi_master_aspeed *aspeed =\n \t\tto_fsi_master_aspeed(to_fsi_master(dev));\n \n+\tif (aspeed->irq_domain)\n+\t\tirq_domain_remove(aspeed->irq_domain);\n+\n \tregmap_exit(aspeed->master.map);\n \tkfree(aspeed);\n }\n@@ -477,6 +551,7 @@ static int fsi_master_aspeed_probe(struct platform_device *pdev)\n \tstruct resource *res;\n \tunsigned int reg;\n \tint rc, links;\n+\tint irq;\n \n \trc = tacoma_cabled_fsi_fixup(&pdev->dev);\n \tif (rc) {\n@@ -567,11 +642,12 @@ static int fsi_master_aspeed_probe(struct platform_device *pdev)\n \taspeed->master.dev.of_node = of_node_get(dev_of_node(&pdev->dev));\n \n \taspeed->master.n_links = links;\n-\taspeed->master.flags = FSI_MASTER_FLAG_RELA;\n+\taspeed->master.flags = FSI_MASTER_FLAG_INTERRUPT | FSI_MASTER_FLAG_RELA;\n \taspeed->master.read = aspeed_master_read;\n \taspeed->master.write = aspeed_master_write;\n \taspeed->master.send_break = aspeed_master_break;\n \taspeed->master.term = aspeed_master_term;\n+\taspeed->master.link_enable = aspeed_master_link_enable;\n \n \tdev_set_drvdata(&pdev->dev, aspeed);\n \n@@ -579,9 +655,30 @@ static int fsi_master_aspeed_probe(struct platform_device *pdev)\n \tif (rc)\n \t\tgoto err_regmap;\n \n+\tirq = platform_get_irq(pdev, 0);\n+\tif (irq > 0) {\n+\t\tunsigned int size = links * FSI_IRQ_COUNT;\n+\n+\t\taspeed->irq_domain = irq_domain_add_linear(aspeed->dev->of_node, size,\n+\t\t\t\t\t\t\t &aspeed_master_irq_domain_ops, aspeed);\n+\t\tif (aspeed->irq_domain) {\n+\t\t\trc = devm_request_irq(aspeed->dev, irq, aspeed_master_irq, 0,\n+\t\t\t\t\t dev_name(aspeed->dev), aspeed);\n+\t\t\tif (rc) {\n+\t\t\t\tdev_warn(aspeed->dev, \"failed to request irq:%d\\n\", irq);\n+\t\t\t\tirq_domain_remove(aspeed->irq_domain);\n+\t\t\t\taspeed->irq_domain = NULL;\n+\t\t\t} else {\n+\t\t\t\tdev_info(aspeed->dev, \"enabling interrupts irq:%d\\n\", irq);\n+\t\t\t}\n+\t\t} else {\n+\t\t\tdev_warn(aspeed->dev, \"failed to create irq domain\\n\");\n+\t\t}\n+\t}\n+\n \trc = fsi_master_register(&aspeed->master);\n \tif (rc)\n-\t\tgoto err_regmap;\n+\t\tgoto err_irq;\n \n \t/* At this point, fsi_master_register performs the device_initialize(),\n \t * and holds the sole reference on master.dev. This means the device\n@@ -593,6 +690,9 @@ static int fsi_master_aspeed_probe(struct platform_device *pdev)\n \tget_device(&aspeed->master.dev);\n \treturn 0;\n \n+err_irq:\n+\tif (aspeed->irq_domain)\n+\t\tirq_domain_remove(aspeed->irq_domain);\n err_regmap:\n \tregmap_exit(aspeed->master.map);\n err_release:\ndiff --git a/include/trace/events/fsi_master_aspeed.h b/include/trace/events/fsi_master_aspeed.h\nindex 7eeecbfec7f09..dba1776334a0e 100644\n--- a/include/trace/events/fsi_master_aspeed.h\n+++ b/include/trace/events/fsi_master_aspeed.h\n@@ -8,6 +8,18 @@\n \n #include \n \n+TRACE_EVENT(fsi_master_aspeed_irq,\n+\tTP_PROTO(uint32_t status),\n+\tTP_ARGS(status),\n+\tTP_STRUCT__entry(\n+\t\t__field(uint32_t, status)\n+\t),\n+\tTP_fast_assign(\n+\t\t__entry->status = status;\n+\t),\n+\tTP_printk(\"status %08x\", __entry->status)\n+);\n+\n TRACE_EVENT(fsi_master_aspeed_opb_xfer,\n \tTP_PROTO(uint32_t addr, uint32_t size, uint32_t data, bool read),\n \tTP_ARGS(addr, size, data, read),\n","prefixes":["v3","24/40"]}