{"id":1886149,"url":"http://patchwork.ozlabs.org/api/patches/1886149/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-gpio/patch/20240112142621.13525-3-prabhakar.mahadev-lad.rj@bp.renesas.com/","project":{"id":42,"url":"http://patchwork.ozlabs.org/api/projects/42/?format=json","name":"Linux GPIO development","link_name":"linux-gpio","list_id":"linux-gpio.vger.kernel.org","list_email":"linux-gpio@vger.kernel.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20240112142621.13525-3-prabhakar.mahadev-lad.rj@bp.renesas.com>","list_archive_url":null,"date":"2024-01-12T14:26:19","name":"[v4,2/4] pinctrl: renesas: rzg2l: Include pinmap in RZG2L_GPIO_PORT_PACK() macro","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"3333a7c60d0eeb5dbfcf70308ca343b52783b18a","submitter":{"id":9539,"url":"http://patchwork.ozlabs.org/api/people/9539/?format=json","name":"Lad, Prabhakar","email":"prabhakar.csengg@gmail.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/linux-gpio/patch/20240112142621.13525-3-prabhakar.mahadev-lad.rj@bp.renesas.com/mbox/","series":[{"id":390295,"url":"http://patchwork.ozlabs.org/api/series/390295/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-gpio/list/?series=390295","date":"2024-01-12T14:26:17","name":"Add missing port pins for RZ/Five SoC","version":4,"mbox":"http://patchwork.ozlabs.org/series/390295/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/1886149/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/1886149/checks/","tags":{},"related":[],"headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-gpio@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20230601 header.b=h308BKFn;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2604:1380:4601:e00::3; helo=am.mirrors.kernel.org;\n envelope-from=linux-gpio+bounces-2167-incoming=patchwork.ozlabs.org@vger.kernel.org;\n receiver=patchwork.ozlabs.org)","smtp.subspace.kernel.org;\n\tdkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com\n header.b=\"h308BKFn\"","smtp.subspace.kernel.org;\n dmarc=pass (p=none dis=none) header.from=gmail.com","smtp.subspace.kernel.org;\n spf=pass smtp.mailfrom=gmail.com"],"Received":["from am.mirrors.kernel.org (am.mirrors.kernel.org\n [IPv6:2604:1380:4601:e00::3])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange X25519 server-signature ECDSA (secp384r1))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4TBP4L3b52z1yPm\n\tfor ; Sat, 13 Jan 2024 01:26:58 +1100 (AEDT)","from smtp.subspace.kernel.org (wormhole.subspace.kernel.org\n [52.25.139.140])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby am.mirrors.kernel.org (Postfix) with ESMTPS id 2C5BE1F21737\n\tfor ; Fri, 12 Jan 2024 14:26:56 +0000 (UTC)","from localhost.localdomain (localhost.localdomain [127.0.0.1])\n\tby smtp.subspace.kernel.org (Postfix) with ESMTP id 983F46E2B6;\n\tFri, 12 Jan 2024 14:26:33 +0000 (UTC)","from mail-wr1-f50.google.com (mail-wr1-f50.google.com\n [209.85.221.50])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits))\n\t(No client certificate requested)\n\tby smtp.subspace.kernel.org (Postfix) with ESMTPS id 8D0586DCFC;\n\tFri, 12 Jan 2024 14:26:31 +0000 (UTC)","by mail-wr1-f50.google.com with SMTP id\n ffacd0b85a97d-336dcebcdb9so5804343f8f.1;\n Fri, 12 Jan 2024 06:26:31 -0800 (PST)","from prasmi.home ([2a00:23c8:2500:a01:494d:c489:3d96:1b15])\n by smtp.gmail.com with ESMTPSA id\n f6-20020a5d4dc6000000b00336a2566aa2sm4021219wru.61.2024.01.12.06.26.28\n (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256);\n Fri, 12 Jan 2024 06:26:28 -0800 (PST)"],"DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=gmail.com; s=20230601; t=1705069590; x=1705674390;\n darn=vger.kernel.org;\n h=content-transfer-encoding:mime-version:references:in-reply-to\n :message-id:date:subject:cc:to:from:from:to:cc:subject:date\n :message-id:reply-to;\n bh=5vxvlXFuuCYceUrSSXVyWc3C7FFvRUyuH+j4HoqKX8o=;\n b=h308BKFnlVPcSyEc0Wr62zzwWEqOKh9uI+0nynknUUy/3J/ES1OnzhXJxRjcqfmiyo\n a7qmHd0MbqDmqwCDL08m7G60aZywsXdD5S62L9SzyisNccGkEBAK3qXm8sz9DPk6TpiH\n Sr7SQACCE6Qb2iWJ+O93UU0FyTxh5cdlMYVbSjxHy8OhojsQT2uYNzdqf6TwSdGEuG28\n RYeGuqQv4cna+ZYqYTmj9DKzH9xTqyaSM23Os6ZheDpobVN5TJ5E8pRTLburO523tHwD\n BsnGBhFHZUCifLnCBCaAzOpuUaOkaOfhhhJ+QTEX4D5Oq0lPylENo+K5I88AzkT9lqBb\n VCIQ==","X-Google-DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=1e100.net; s=20230601; t=1705069590; x=1705674390;\n h=content-transfer-encoding:mime-version:references:in-reply-to\n :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc\n :subject:date:message-id:reply-to;\n bh=5vxvlXFuuCYceUrSSXVyWc3C7FFvRUyuH+j4HoqKX8o=;\n b=pdzi4JcG+XA1MlbItRTagLm1f0Q5cNC2SqWKpeoK0vP/rGCpXtnv4v6LfaxKNWMlxo\n Sb+RTpK0v3SYAJKe++koD712B5QSm+piMk3slZyOsgf/0Q6RBbl9XfqW7DdvjHK2MDbE\n /i0mrXUWnElUs4kW4f3s47X7gDHJ8mfT41JNdjXUIW2avIegghm2zs8DSqEvl1c73rWg\n loLyqTy4sVJMOG8hRWUTuZ/ZIYSlVgUSzpXu6/TUBDRmpYlQYAp7u0vRmR1CMrLbkPQN\n +NzugrL1VOqMDDCXt8MT0zkKzFVxTXjhrLx7ofxCTiGkTakh4SZ2QgB9IHhPftlhLcBt\n yYqA==","X-Gm-Message-State":"AOJu0YzarT91AEjmQeUg/KSzT7D4PqqmTjB5dFQZwpxrEpxwh4I8n2Ev\n\t8IqCQuDaCL8vzhpsvZxYCgsTAVgo5HyxZQ==","X-Google-Smtp-Source":"\n AGHT+IFncPnXA9u6rY15e/Wbp8htdpSvTCv2F1AL969KROSyRuqFKLHUmVwpRrLlwSciJy7WSTLSdA==","X-Received":"by 2002:a5d:4d12:0:b0:336:8d2e:729d with SMTP id\n z18-20020a5d4d12000000b003368d2e729dmr422610wrt.121.1705069589675;\n Fri, 12 Jan 2024 06:26:29 -0800 (PST)","From":"Prabhakar ","X-Google-Original-From":"Prabhakar ","To":"Geert Uytterhoeven ,\n\tMagnus Damm ,\n\tLinus Walleij ","Cc":"Rob Herring ,\n\tKrzysztof Kozlowski ,\n\tConor Dooley ,\n\tlinux-renesas-soc@vger.kernel.org,\n\tdevicetree@vger.kernel.org,\n\tlinux-riscv@lists.infradead.org,\n\tlinux-kernel@vger.kernel.org,\n\tlinux-gpio@vger.kernel.org,\n\tPrabhakar ,\n\tBiju Das ,\n\tClaudiu Beznea ,\n\tLad Prabhakar ","Subject":"[PATCH v4 2/4] pinctrl: renesas: rzg2l: Include pinmap in\n RZG2L_GPIO_PORT_PACK() macro","Date":"Fri, 12 Jan 2024 14:26:19 +0000","Message-Id":"<20240112142621.13525-3-prabhakar.mahadev-lad.rj@bp.renesas.com>","X-Mailer":"git-send-email 2.34.1","In-Reply-To":"<20240112142621.13525-1-prabhakar.mahadev-lad.rj@bp.renesas.com>","References":"<20240112142621.13525-1-prabhakar.mahadev-lad.rj@bp.renesas.com>","Precedence":"bulk","X-Mailing-List":"linux-gpio@vger.kernel.org","List-Id":"","List-Subscribe":"","List-Unsubscribe":"","MIME-Version":"1.0","Content-Transfer-Encoding":"8bit"},"content":"From: Lad Prabhakar \n\nCurrently we assume all the port pins are sequential ie always PX_0 to\nPX_n (n=1..7) exist, but on RZ/Five SoC we have additional pins P19_1 to\nP28_5 which have holes in them, for example only one pin on port19 is\navailable and that is P19_1 and not P19_0. So to handle such cases\ninclude pinmap for each port which would indicate the pin availability\non each port. As the pincount can be calculated based on pinmap drop this\nfrom RZG2L_GPIO_PORT_PACK() macro.\n\nPreviously we had a max of 7 pins on each port but on RZ/Five Port-20\nhas 8 pins, so move the single pin configuration to BIT(63).\n\nSigned-off-by: Lad Prabhakar \n---\n drivers/pinctrl/renesas/pinctrl-rzg2l.c | 56 +++++++++++++------------\n 1 file changed, 29 insertions(+), 27 deletions(-)","diff":"diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c\nindex fee348b80892..8b8644d2c355 100644\n--- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c\n+++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c\n@@ -80,19 +80,20 @@\n * n indicates number of pins in the port, a is the register index\n * and f is pin configuration capabilities supported.\n */\n-#define PIN_CFG_PIN_CNT_MASK\t\tGENMASK(30, 28)\n+#define PIN_CFG_PIN_MAP_MASK\t\tGENMASK(35, 28)\n #define PIN_CFG_PIN_REG_MASK\t\tGENMASK(27, 20)\n #define PIN_CFG_MASK\t\t\tGENMASK(19, 0)\n-#define RZG2L_GPIO_PORT_PACK(n, a, f)\t(FIELD_PREP_CONST(PIN_CFG_PIN_CNT_MASK, (n)) | \\\n+\n+#define RZG2L_GPIO_PORT_PACK(n, a, f)\t((((1ULL << (n)) - 1) << 28) | \\\n \t\t\t\t\t FIELD_PREP_CONST(PIN_CFG_PIN_REG_MASK, (a)) | \\\n \t\t\t\t\t FIELD_PREP_CONST(PIN_CFG_MASK, (f)))\n \n /*\n- * BIT(31) indicates dedicated pin, p is the register index while\n+ * BIT(63) indicates dedicated pin, p is the register index while\n * referencing to SR/IEN/IOLH/FILxx registers, b is the register bits\n * (b * 8) and f is the pin configuration capabilities supported.\n */\n-#define RZG2L_SINGLE_PIN\t\tBIT(31)\n+#define RZG2L_SINGLE_PIN\t\tBIT_ULL(63)\n #define RZG2L_SINGLE_PIN_INDEX_MASK\tGENMASK(30, 24)\n #define RZG2L_SINGLE_PIN_BITS_MASK\tGENMASK(22, 20)\n \n@@ -196,12 +197,12 @@ struct rzg2l_hwcfg {\n \n struct rzg2l_dedicated_configs {\n \tconst char *name;\n-\tu32 config;\n+\tu64 config;\n };\n \n struct rzg2l_pinctrl_data {\n \tconst char * const *port_pins;\n-\tconst u32 *port_pin_configs;\n+\tconst u64 *port_pin_configs;\n \tunsigned int n_ports;\n \tconst struct rzg2l_dedicated_configs *dedicated_pins;\n \tunsigned int n_port_pins;\n@@ -302,7 +303,7 @@ static int rzg2l_pinctrl_set_mux(struct pinctrl_dev *pctldev,\n \tpins = group->pins;\n \n \tfor (i = 0; i < group->num_pins; i++) {\n-\t\tunsigned int *pin_data = pctrl->desc.pins[pins[i]].drv_data;\n+\t\tu64 *pin_data = pctrl->desc.pins[pins[i]].drv_data;\n \t\tu32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data);\n \t\tu32 pin = RZG2L_PIN_ID_TO_PIN(pins[i]);\n \n@@ -565,13 +566,13 @@ static int rzg2l_dt_node_to_map(struct pinctrl_dev *pctldev,\n }\n \n static int rzg2l_validate_gpio_pin(struct rzg2l_pinctrl *pctrl,\n-\t\t\t\t u32 cfg, u32 port, u8 bit)\n+\t\t\t\t u64 cfg, u32 port, u8 bit)\n {\n-\tu8 pincount = FIELD_GET(PIN_CFG_PIN_CNT_MASK, cfg);\n+\tu8 pinmap = FIELD_GET(PIN_CFG_PIN_MAP_MASK, cfg);\n \tu32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(cfg);\n-\tu32 data;\n+\tu64 data;\n \n-\tif (bit >= pincount || port >= pctrl->data->n_port_pins)\n+\tif (!(pinmap & BIT(bit)) || port >= pctrl->data->n_port_pins)\n \t\treturn -EINVAL;\n \n \tdata = pctrl->data->port_pin_configs[port];\n@@ -863,7 +864,7 @@ static int rzg2l_pinctrl_pinconf_get(struct pinctrl_dev *pctldev,\n \tenum pin_config_param param = pinconf_to_config_param(*config);\n \tconst struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg;\n \tconst struct pinctrl_pin_desc *pin = &pctrl->desc.pins[_pin];\n-\tunsigned int *pin_data = pin->drv_data;\n+\tu64 *pin_data = pin->drv_data;\n \tunsigned int arg = 0;\n \tu32 off, cfg;\n \tint ret;\n@@ -966,7 +967,7 @@ static int rzg2l_pinctrl_pinconf_set(struct pinctrl_dev *pctldev,\n \tconst struct pinctrl_pin_desc *pin = &pctrl->desc.pins[_pin];\n \tconst struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg;\n \tstruct rzg2l_pinctrl_pin_settings settings = pctrl->settings[_pin];\n-\tunsigned int *pin_data = pin->drv_data;\n+\tu64 *pin_data = pin->drv_data;\n \tenum pin_config_param param;\n \tunsigned int i, arg, index;\n \tu32 cfg, off;\n@@ -1171,7 +1172,7 @@ static int rzg2l_gpio_request(struct gpio_chip *chip, unsigned int offset)\n {\n \tstruct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip);\n \tconst struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[offset];\n-\tu32 *pin_data = pin_desc->drv_data;\n+\tu64 *pin_data = pin_desc->drv_data;\n \tu32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data);\n \tu32 port = RZG2L_PIN_ID_TO_PORT(offset);\n \tu8 bit = RZG2L_PIN_ID_TO_PIN(offset);\n@@ -1203,7 +1204,7 @@ static void rzg2l_gpio_set_direction(struct rzg2l_pinctrl *pctrl, u32 offset,\n \t\t\t\t bool output)\n {\n \tconst struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[offset];\n-\tunsigned int *pin_data = pin_desc->drv_data;\n+\tu64 *pin_data = pin_desc->drv_data;\n \tu32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data);\n \tu8 bit = RZG2L_PIN_ID_TO_PIN(offset);\n \tunsigned long flags;\n@@ -1224,7 +1225,7 @@ static int rzg2l_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)\n {\n \tstruct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip);\n \tconst struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[offset];\n-\tunsigned int *pin_data = pin_desc->drv_data;\n+\tu64 *pin_data = pin_desc->drv_data;\n \tu32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data);\n \tu8 bit = RZG2L_PIN_ID_TO_PIN(offset);\n \n@@ -1255,7 +1256,7 @@ static void rzg2l_gpio_set(struct gpio_chip *chip, unsigned int offset,\n {\n \tstruct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip);\n \tconst struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[offset];\n-\tunsigned int *pin_data = pin_desc->drv_data;\n+\tu64 *pin_data = pin_desc->drv_data;\n \tu32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data);\n \tu8 bit = RZG2L_PIN_ID_TO_PIN(offset);\n \tunsigned long flags;\n@@ -1288,7 +1289,7 @@ static int rzg2l_gpio_get(struct gpio_chip *chip, unsigned int offset)\n {\n \tstruct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip);\n \tconst struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[offset];\n-\tunsigned int *pin_data = pin_desc->drv_data;\n+\tu64 *pin_data = pin_desc->drv_data;\n \tu32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data);\n \tu8 bit = RZG2L_PIN_ID_TO_PIN(offset);\n \tu16 reg16;\n@@ -1373,7 +1374,7 @@ static const char * const rzg2l_gpio_names[] = {\n \t\"P48_0\", \"P48_1\", \"P48_2\", \"P48_3\", \"P48_4\", \"P48_5\", \"P48_6\", \"P48_7\",\n };\n \n-static const u32 r9a07g044_gpio_configs[] = {\n+static const u64 r9a07g044_gpio_configs[] = {\n \tRZG2L_GPIO_PORT_PACK(2, 0x10, RZG2L_MPXED_PIN_FUNCS),\n \tRZG2L_GPIO_PORT_PACK(2, 0x11, RZG2L_MPXED_PIN_FUNCS),\n \tRZG2L_GPIO_PORT_PACK(2, 0x12, RZG2L_MPXED_PIN_FUNCS),\n@@ -1425,7 +1426,7 @@ static const u32 r9a07g044_gpio_configs[] = {\n \tRZG2L_GPIO_PORT_PACK(5, 0x40, RZG2L_MPXED_PIN_FUNCS),\n };\n \n-static const u32 r9a07g043_gpio_configs[] = {\n+static const u64 r9a07g043_gpio_configs[] = {\n \tRZG2L_GPIO_PORT_PACK(4, 0x10, RZG2L_MPXED_PIN_FUNCS),\n \tRZG2L_GPIO_PORT_PACK(5, 0x11, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),\n \tRZG2L_GPIO_PORT_PACK(4, 0x12, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),\n@@ -1447,7 +1448,7 @@ static const u32 r9a07g043_gpio_configs[] = {\n \tRZG2L_GPIO_PORT_PACK(6, 0x22, RZG2L_MPXED_PIN_FUNCS),\n };\n \n-static const u32 r9a08g045_gpio_configs[] = {\n+static const u64 r9a08g045_gpio_configs[] = {\n \tRZG2L_GPIO_PORT_PACK(4, 0x20, RZG3S_MPXED_PIN_FUNCS(A)),\t\t\t/* P0 */\n \tRZG2L_GPIO_PORT_PACK(5, 0x30, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C |\n \t\t\t\t\t\t\t\tPIN_CFG_IO_VMC_ETH0)) |\n@@ -1615,12 +1616,12 @@ static int rzg2l_gpio_get_gpioint(unsigned int virq, const struct rzg2l_pinctrl_\n \tbit = virq % 8;\n \n \tif (port >= data->n_ports ||\n-\t bit >= FIELD_GET(PIN_CFG_PIN_CNT_MASK, data->port_pin_configs[port]))\n+\t bit >= hweight8(FIELD_GET(PIN_CFG_PIN_MAP_MASK, data->port_pin_configs[port])))\n \t\treturn -EINVAL;\n \n \tgpioint = bit;\n \tfor (i = 0; i < port; i++)\n-\t\tgpioint += FIELD_GET(PIN_CFG_PIN_CNT_MASK, data->port_pin_configs[i]);\n+\t\tgpioint += hweight8(FIELD_GET(PIN_CFG_PIN_MAP_MASK, data->port_pin_configs[i]));\n \n \treturn gpioint;\n }\n@@ -1631,7 +1632,7 @@ static void rzg2l_gpio_irq_disable(struct irq_data *d)\n \tstruct rzg2l_pinctrl *pctrl = container_of(gc, struct rzg2l_pinctrl, gpio_chip);\n \tunsigned int hwirq = irqd_to_hwirq(d);\n \tconst struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[hwirq];\n-\tunsigned int *pin_data = pin_desc->drv_data;\n+\tu64 *pin_data = pin_desc->drv_data;\n \tu32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data);\n \tu8 bit = RZG2L_PIN_ID_TO_PIN(hwirq);\n \tunsigned long flags;\n@@ -1658,7 +1659,7 @@ static void rzg2l_gpio_irq_enable(struct irq_data *d)\n \tstruct rzg2l_pinctrl *pctrl = container_of(gc, struct rzg2l_pinctrl, gpio_chip);\n \tunsigned int hwirq = irqd_to_hwirq(d);\n \tconst struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[hwirq];\n-\tunsigned int *pin_data = pin_desc->drv_data;\n+\tu64 *pin_data = pin_desc->drv_data;\n \tu32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data);\n \tu8 bit = RZG2L_PIN_ID_TO_PIN(hwirq);\n \tunsigned long flags;\n@@ -1795,7 +1796,8 @@ static void rzg2l_init_irq_valid_mask(struct gpio_chip *gc,\n \t\tbit = offset % 8;\n \n \t\tif (port >= pctrl->data->n_ports ||\n-\t\t bit >= FIELD_GET(PIN_CFG_PIN_CNT_MASK, pctrl->data->port_pin_configs[port]))\n+\t\t bit >= hweight8(FIELD_GET(PIN_CFG_PIN_MAP_MASK,\n+\t\t\t\t\t pctrl->data->port_pin_configs[port])))\n \t\t\tclear_bit(offset, valid_mask);\n \t}\n }\n@@ -1877,7 +1879,7 @@ static int rzg2l_pinctrl_register(struct rzg2l_pinctrl *pctrl)\n \tconst struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg;\n \tstruct pinctrl_pin_desc *pins;\n \tunsigned int i, j;\n-\tu32 *pin_data;\n+\tu64 *pin_data;\n \tint ret;\n \n \tpctrl->desc.name = DRV_NAME;\n","prefixes":["v4","2/4"]}