{"id":1882131,"url":"http://patchwork.ozlabs.org/api/patches/1882131/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20240103173349.398526-25-alex.bennee@linaro.org/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20240103173349.398526-25-alex.bennee@linaro.org>","list_archive_url":null,"date":"2024-01-03T17:33:30","name":"[v2,24/43] target/riscv: Move misa_mxl_max to class","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"481b029f6eb17a1120671472a6b896e74bfb383e","submitter":{"id":39532,"url":"http://patchwork.ozlabs.org/api/people/39532/?format=json","name":"Alex Bennée","email":"alex.bennee@linaro.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20240103173349.398526-25-alex.bennee@linaro.org/mbox/","series":[{"id":388742,"url":"http://patchwork.ozlabs.org/api/series/388742/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=388742","date":"2024-01-03T17:33:08","name":"testing and plugin updates for 9.0 (pre-PR)","version":2,"mbox":"http://patchwork.ozlabs.org/series/388742/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/1882131/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/1882131/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=P+h5jLcd;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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Iglesias\" ,\n Eduardo Habkost ,\n Pierrick Bouvier , qemu-riscv@nongnu.org,\n Alistair Francis ,\n Akihiko Odaki ","Subject":"[PATCH v2 24/43] target/riscv: Move misa_mxl_max to class","Date":"Wed, 3 Jan 2024 17:33:30 +0000","Message-Id":"<20240103173349.398526-25-alex.bennee@linaro.org>","X-Mailer":"git-send-email 2.39.2","In-Reply-To":"<20240103173349.398526-1-alex.bennee@linaro.org>","References":"<20240103173349.398526-1-alex.bennee@linaro.org>","MIME-Version":"1.0","Content-Type":"text/plain; charset=UTF-8","Content-Transfer-Encoding":"8bit","Received-SPF":"pass client-ip=2a00:1450:4864:20::42d;\n envelope-from=alex.bennee@linaro.org; helo=mail-wr1-x42d.google.com","X-Spam_score_int":"-20","X-Spam_score":"-2.1","X-Spam_bar":"--","X-Spam_report":"(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001,\n T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"From: Akihiko Odaki \n\nmisa_mxl_max is common for all instances of a RISC-V CPU class so they\nare better put into class.\n\nSigned-off-by: Akihiko Odaki \nMessage-Id: <20231213-riscv-v7-3-a760156a337f@daynix.com>\nSigned-off-by: Alex Bennée \n---\n target/riscv/cpu.h | 4 +-\n target/riscv/cpu.c | 118 +++++++++++++++++++------------------\n target/riscv/gdbstub.c | 12 ++--\n target/riscv/kvm/kvm-cpu.c | 10 ++--\n target/riscv/machine.c | 7 +--\n target/riscv/tcg/tcg-cpu.c | 12 ++--\n target/riscv/translate.c | 3 +-\n 7 files changed, 87 insertions(+), 79 deletions(-)","diff":"diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h\nindex d74b361be64..060b7f69a74 100644\n--- a/target/riscv/cpu.h\n+++ b/target/riscv/cpu.h\n@@ -169,7 +169,6 @@ struct CPUArchState {\n \n /* RISCVMXL, but uint32_t for vmstate migration */\n uint32_t misa_mxl; /* current mxl */\n- uint32_t misa_mxl_max; /* max mxl for this cpu */\n uint32_t misa_ext; /* current extensions */\n uint32_t misa_ext_mask; /* max ext for this cpu */\n uint32_t xl; /* current xlen */\n@@ -450,6 +449,7 @@ struct RISCVCPUClass {\n \n DeviceRealize parent_realize;\n ResettablePhases parent_phases;\n+ uint32_t misa_mxl_max; /* max mxl for this cpu */\n };\n \n static inline int riscv_has_ext(CPURISCVState *env, target_ulong ext)\n@@ -756,7 +756,7 @@ enum riscv_pmu_event_idx {\n /* used by tcg/tcg-cpu.c*/\n void isa_ext_update_enabled(RISCVCPU *cpu, uint32_t ext_offset, bool en);\n bool isa_ext_is_enabled(RISCVCPU *cpu, uint32_t ext_offset);\n-void riscv_cpu_set_misa(CPURISCVState *env, RISCVMXL mxl, uint32_t ext);\n+void riscv_cpu_set_misa_ext(CPURISCVState *env, uint32_t ext);\n \n typedef struct RISCVCPUMultiExtConfig {\n const char *name;\ndiff --git a/target/riscv/cpu.c b/target/riscv/cpu.c\nindex 83c7c0cf07b..2ab61df2217 100644\n--- a/target/riscv/cpu.c\n+++ b/target/riscv/cpu.c\n@@ -274,9 +274,8 @@ const char *riscv_cpu_get_trap_name(target_ulong cause, bool async)\n }\n }\n \n-void riscv_cpu_set_misa(CPURISCVState *env, RISCVMXL mxl, uint32_t ext)\n+void riscv_cpu_set_misa_ext(CPURISCVState *env, uint32_t ext)\n {\n- env->misa_mxl_max = env->misa_mxl = mxl;\n env->misa_ext_mask = env->misa_ext = ext;\n }\n \n@@ -378,11 +377,7 @@ static void riscv_any_cpu_init(Object *obj)\n {\n RISCVCPU *cpu = RISCV_CPU(obj);\n CPURISCVState *env = &cpu->env;\n-#if defined(TARGET_RISCV32)\n- riscv_cpu_set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVU);\n-#elif defined(TARGET_RISCV64)\n- riscv_cpu_set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVU);\n-#endif\n+ riscv_cpu_set_misa_ext(env, RVI | RVM | RVA | RVF | RVD | RVC | RVU);\n \n #ifndef CONFIG_USER_ONLY\n set_satp_mode_max_supported(RISCV_CPU(obj),\n@@ -403,16 +398,14 @@ static void riscv_max_cpu_init(Object *obj)\n {\n RISCVCPU *cpu = RISCV_CPU(obj);\n CPURISCVState *env = &cpu->env;\n- RISCVMXL mlx = MXL_RV64;\n \n-#ifdef TARGET_RISCV32\n- mlx = MXL_RV32;\n-#endif\n- riscv_cpu_set_misa(env, mlx, 0);\n env->priv_ver = PRIV_VERSION_LATEST;\n #ifndef CONFIG_USER_ONLY\n- set_satp_mode_max_supported(RISCV_CPU(obj), mlx == MXL_RV32 ?\n- VM_1_10_SV32 : VM_1_10_SV57);\n+#ifdef TARGET_RISCV32\n+ set_satp_mode_max_supported(cpu, VM_1_10_SV32);\n+#else\n+ set_satp_mode_max_supported(cpu, VM_1_10_SV57);\n+#endif\n #endif\n }\n \n@@ -420,8 +413,6 @@ static void riscv_max_cpu_init(Object *obj)\n static void rv64_base_cpu_init(Object *obj)\n {\n CPURISCVState *env = &RISCV_CPU(obj)->env;\n- /* We set this in the realise function */\n- riscv_cpu_set_misa(env, MXL_RV64, 0);\n /* Set latest version of privileged specification */\n env->priv_ver = PRIV_VERSION_LATEST;\n #ifndef CONFIG_USER_ONLY\n@@ -433,8 +424,7 @@ static void rv64_sifive_u_cpu_init(Object *obj)\n {\n RISCVCPU *cpu = RISCV_CPU(obj);\n CPURISCVState *env = &cpu->env;\n- riscv_cpu_set_misa(env, MXL_RV64,\n- RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);\n+ riscv_cpu_set_misa_ext(env, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);\n env->priv_ver = PRIV_VERSION_1_10_0;\n #ifndef CONFIG_USER_ONLY\n set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV39);\n@@ -452,7 +442,7 @@ static void rv64_sifive_e_cpu_init(Object *obj)\n CPURISCVState *env = &RISCV_CPU(obj)->env;\n RISCVCPU *cpu = RISCV_CPU(obj);\n \n- riscv_cpu_set_misa(env, MXL_RV64, RVI | RVM | RVA | RVC | RVU);\n+ riscv_cpu_set_misa_ext(env, RVI | RVM | RVA | RVC | RVU);\n env->priv_ver = PRIV_VERSION_1_10_0;\n #ifndef CONFIG_USER_ONLY\n set_satp_mode_max_supported(cpu, VM_1_10_MBARE);\n@@ -469,7 +459,7 @@ static void rv64_thead_c906_cpu_init(Object *obj)\n CPURISCVState *env = &RISCV_CPU(obj)->env;\n RISCVCPU *cpu = RISCV_CPU(obj);\n \n- riscv_cpu_set_misa(env, MXL_RV64, RVG | RVC | RVS | RVU);\n+ riscv_cpu_set_misa_ext(env, RVG | RVC | RVS | RVU);\n env->priv_ver = PRIV_VERSION_1_11_0;\n \n cpu->cfg.ext_zfa = true;\n@@ -500,7 +490,7 @@ static void rv64_veyron_v1_cpu_init(Object *obj)\n CPURISCVState *env = &RISCV_CPU(obj)->env;\n RISCVCPU *cpu = RISCV_CPU(obj);\n \n- riscv_cpu_set_misa(env, MXL_RV64, RVG | RVC | RVS | RVU | RVH);\n+ riscv_cpu_set_misa_ext(env, RVG | RVC | RVS | RVU | RVH);\n env->priv_ver = PRIV_VERSION_1_12_0;\n \n /* Enable ISA extensions */\n@@ -544,8 +534,6 @@ static void rv128_base_cpu_init(Object *obj)\n exit(EXIT_FAILURE);\n }\n CPURISCVState *env = &RISCV_CPU(obj)->env;\n- /* We set this in the realise function */\n- riscv_cpu_set_misa(env, MXL_RV128, 0);\n /* Set latest version of privileged specification */\n env->priv_ver = PRIV_VERSION_LATEST;\n #ifndef CONFIG_USER_ONLY\n@@ -556,8 +544,6 @@ static void rv128_base_cpu_init(Object *obj)\n static void rv32_base_cpu_init(Object *obj)\n {\n CPURISCVState *env = &RISCV_CPU(obj)->env;\n- /* We set this in the realise function */\n- riscv_cpu_set_misa(env, MXL_RV32, 0);\n /* Set latest version of privileged specification */\n env->priv_ver = PRIV_VERSION_LATEST;\n #ifndef CONFIG_USER_ONLY\n@@ -569,8 +555,7 @@ static void rv32_sifive_u_cpu_init(Object *obj)\n {\n RISCVCPU *cpu = RISCV_CPU(obj);\n CPURISCVState *env = &cpu->env;\n- riscv_cpu_set_misa(env, MXL_RV32,\n- RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);\n+ riscv_cpu_set_misa_ext(env, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);\n env->priv_ver = PRIV_VERSION_1_10_0;\n #ifndef CONFIG_USER_ONLY\n set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV32);\n@@ -588,7 +573,7 @@ static void rv32_sifive_e_cpu_init(Object *obj)\n CPURISCVState *env = &RISCV_CPU(obj)->env;\n RISCVCPU *cpu = RISCV_CPU(obj);\n \n- riscv_cpu_set_misa(env, MXL_RV32, RVI | RVM | RVA | RVC | RVU);\n+ riscv_cpu_set_misa_ext(env, RVI | RVM | RVA | RVC | RVU);\n env->priv_ver = PRIV_VERSION_1_10_0;\n #ifndef CONFIG_USER_ONLY\n set_satp_mode_max_supported(cpu, VM_1_10_MBARE);\n@@ -605,7 +590,7 @@ static void rv32_ibex_cpu_init(Object *obj)\n CPURISCVState *env = &RISCV_CPU(obj)->env;\n RISCVCPU *cpu = RISCV_CPU(obj);\n \n- riscv_cpu_set_misa(env, MXL_RV32, RVI | RVM | RVC | RVU);\n+ riscv_cpu_set_misa_ext(env, RVI | RVM | RVC | RVU);\n env->priv_ver = PRIV_VERSION_1_12_0;\n #ifndef CONFIG_USER_ONLY\n set_satp_mode_max_supported(cpu, VM_1_10_MBARE);\n@@ -622,7 +607,7 @@ static void rv32_imafcu_nommu_cpu_init(Object *obj)\n CPURISCVState *env = &RISCV_CPU(obj)->env;\n RISCVCPU *cpu = RISCV_CPU(obj);\n \n- riscv_cpu_set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVC | RVU);\n+ riscv_cpu_set_misa_ext(env, RVI | RVM | RVA | RVF | RVC | RVU);\n env->priv_ver = PRIV_VERSION_1_10_0;\n #ifndef CONFIG_USER_ONLY\n set_satp_mode_max_supported(cpu, VM_1_10_MBARE);\n@@ -845,7 +830,7 @@ static void riscv_cpu_reset_hold(Object *obj)\n mcc->parent_phases.hold(obj);\n }\n #ifndef CONFIG_USER_ONLY\n- env->misa_mxl = env->misa_mxl_max;\n+ env->misa_mxl = mcc->misa_mxl_max;\n env->priv = PRV_M;\n env->mstatus &= ~(MSTATUS_MIE | MSTATUS_MPRV);\n if (env->misa_mxl > MXL_RV32) {\n@@ -1213,6 +1198,12 @@ static void riscv_cpu_post_init(Object *obj)\n \n static void riscv_cpu_init(Object *obj)\n {\n+ RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(obj);\n+ RISCVCPU *cpu = RISCV_CPU(obj);\n+ CPURISCVState *env = &cpu->env;\n+\n+ env->misa_mxl = mcc->misa_mxl_max;\n+\n #ifndef CONFIG_USER_ONLY\n qdev_init_gpio_in(DEVICE(obj), riscv_cpu_set_irq,\n IRQ_LOCAL_MAX + IRQ_LOCAL_GUEST_MAX);\n@@ -1657,7 +1648,7 @@ static void cpu_get_marchid(Object *obj, Visitor *v, const char *name,\n visit_type_bool(v, name, &value, errp);\n }\n \n-static void riscv_cpu_class_init(ObjectClass *c, void *data)\n+static void riscv_cpu_common_class_init(ObjectClass *c, void *data)\n {\n RISCVCPUClass *mcc = RISCV_CPU_CLASS(c);\n CPUClass *cc = CPU_CLASS(c);\n@@ -1699,6 +1690,13 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data)\n device_class_set_props(dc, riscv_cpu_properties);\n }\n \n+static void riscv_cpu_class_init(ObjectClass *c, void *data)\n+{\n+ RISCVCPUClass *mcc = RISCV_CPU_CLASS(c);\n+\n+ mcc->misa_mxl_max = (uint32_t)(uintptr_t)data;\n+}\n+\n static void riscv_isa_string_ext(RISCVCPU *cpu, char **isa_str,\n int max_str_len)\n {\n@@ -1764,18 +1762,22 @@ void riscv_cpu_list(void)\n g_slist_free(list);\n }\n \n-#define DEFINE_CPU(type_name, initfn) \\\n- { \\\n- .name = type_name, \\\n- .parent = TYPE_RISCV_CPU, \\\n- .instance_init = initfn \\\n+#define DEFINE_CPU(type_name, misa_mxl_max, initfn) \\\n+ { \\\n+ .name = (type_name), \\\n+ .parent = TYPE_RISCV_CPU, \\\n+ .instance_init = (initfn), \\\n+ .class_init = riscv_cpu_class_init, \\\n+ .class_data = (void *)(misa_mxl_max) \\\n }\n \n-#define DEFINE_DYNAMIC_CPU(type_name, initfn) \\\n- { \\\n- .name = type_name, \\\n- .parent = TYPE_RISCV_DYNAMIC_CPU, \\\n- .instance_init = initfn \\\n+#define DEFINE_DYNAMIC_CPU(type_name, misa_mxl_max, initfn) \\\n+ { \\\n+ .name = (type_name), \\\n+ .parent = TYPE_RISCV_DYNAMIC_CPU, \\\n+ .instance_init = (initfn), \\\n+ .class_init = riscv_cpu_class_init, \\\n+ .class_data = (void *)(misa_mxl_max) \\\n }\n \n static const TypeInfo riscv_cpu_type_infos[] = {\n@@ -1788,29 +1790,31 @@ static const TypeInfo riscv_cpu_type_infos[] = {\n .instance_post_init = riscv_cpu_post_init,\n .abstract = true,\n .class_size = sizeof(RISCVCPUClass),\n- .class_init = riscv_cpu_class_init,\n+ .class_init = riscv_cpu_common_class_init,\n },\n {\n .name = TYPE_RISCV_DYNAMIC_CPU,\n .parent = TYPE_RISCV_CPU,\n .abstract = true,\n },\n- DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_ANY, riscv_any_cpu_init),\n- DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_MAX, riscv_max_cpu_init),\n #if defined(TARGET_RISCV32)\n- DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE32, rv32_base_cpu_init),\n- DEFINE_CPU(TYPE_RISCV_CPU_IBEX, rv32_ibex_cpu_init),\n- DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rv32_sifive_e_cpu_init),\n- DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E34, rv32_imafcu_nommu_cpu_init),\n- DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rv32_sifive_u_cpu_init),\n+ DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_ANY, MXL_RV32, riscv_any_cpu_init),\n+ DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_MAX, MXL_RV32, riscv_max_cpu_init),\n+ DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE32, MXL_RV32, rv32_base_cpu_init),\n+ DEFINE_CPU(TYPE_RISCV_CPU_IBEX, MXL_RV32, rv32_ibex_cpu_init),\n+ DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31, MXL_RV32, rv32_sifive_e_cpu_init),\n+ DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E34, MXL_RV32, rv32_imafcu_nommu_cpu_init),\n+ DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34, MXL_RV32, rv32_sifive_u_cpu_init),\n #elif defined(TARGET_RISCV64)\n- DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE64, rv64_base_cpu_init),\n- DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rv64_sifive_e_cpu_init),\n- DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rv64_sifive_u_cpu_init),\n- DEFINE_CPU(TYPE_RISCV_CPU_SHAKTI_C, rv64_sifive_u_cpu_init),\n- DEFINE_CPU(TYPE_RISCV_CPU_THEAD_C906, rv64_thead_c906_cpu_init),\n- DEFINE_CPU(TYPE_RISCV_CPU_VEYRON_V1, rv64_veyron_v1_cpu_init),\n- DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE128, rv128_base_cpu_init),\n+ DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_ANY, MXL_RV64, riscv_any_cpu_init),\n+ DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_MAX, MXL_RV64, riscv_max_cpu_init),\n+ DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE64, MXL_RV64, rv64_base_cpu_init),\n+ DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, MXL_RV64, rv64_sifive_e_cpu_init),\n+ DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, MXL_RV64, rv64_sifive_u_cpu_init),\n+ DEFINE_CPU(TYPE_RISCV_CPU_SHAKTI_C, MXL_RV64, rv64_sifive_u_cpu_init),\n+ DEFINE_CPU(TYPE_RISCV_CPU_THEAD_C906, MXL_RV64, rv64_thead_c906_cpu_init),\n+ DEFINE_CPU(TYPE_RISCV_CPU_VEYRON_V1, MXL_RV64, rv64_veyron_v1_cpu_init),\n+ DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE128, MXL_RV128, rv128_base_cpu_init),\n #endif\n };\n \ndiff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c\nindex 58b3ace0fe9..365040228a1 100644\n--- a/target/riscv/gdbstub.c\n+++ b/target/riscv/gdbstub.c\n@@ -49,6 +49,7 @@ static const struct TypeSize vec_lanes[] = {\n \n int riscv_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)\n {\n+ RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cs);\n RISCVCPU *cpu = RISCV_CPU(cs);\n CPURISCVState *env = &cpu->env;\n target_ulong tmp;\n@@ -61,7 +62,7 @@ int riscv_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)\n return 0;\n }\n \n- switch (env->misa_mxl_max) {\n+ switch (mcc->misa_mxl_max) {\n case MXL_RV32:\n return gdb_get_reg32(mem_buf, tmp);\n case MXL_RV64:\n@@ -75,12 +76,13 @@ int riscv_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)\n \n int riscv_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)\n {\n+ RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cs);\n RISCVCPU *cpu = RISCV_CPU(cs);\n CPURISCVState *env = &cpu->env;\n int length = 0;\n target_ulong tmp;\n \n- switch (env->misa_mxl_max) {\n+ switch (mcc->misa_mxl_max) {\n case MXL_RV32:\n tmp = (int32_t)ldl_p(mem_buf);\n length = 4;\n@@ -214,11 +216,12 @@ static int riscv_gdb_set_virtual(CPURISCVState *cs, uint8_t *mem_buf, int n)\n \n static int riscv_gen_dynamic_csr_xml(CPUState *cs, int base_reg)\n {\n+ RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cs);\n RISCVCPU *cpu = RISCV_CPU(cs);\n CPURISCVState *env = &cpu->env;\n GString *s = g_string_new(NULL);\n riscv_csr_predicate_fn predicate;\n- int bitsize = 16 << env->misa_mxl_max;\n+ int bitsize = 16 << mcc->misa_mxl_max;\n int i;\n \n #if !defined(CONFIG_USER_ONLY)\n@@ -310,6 +313,7 @@ static int ricsv_gen_dynamic_vector_xml(CPUState *cs, int base_reg)\n \n void riscv_cpu_register_gdb_regs_for_features(CPUState *cs)\n {\n+ RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cs);\n RISCVCPU *cpu = RISCV_CPU(cs);\n CPURISCVState *env = &cpu->env;\n if (env->misa_ext & RVD) {\n@@ -326,7 +330,7 @@ void riscv_cpu_register_gdb_regs_for_features(CPUState *cs)\n ricsv_gen_dynamic_vector_xml(cs, base_reg),\n \"riscv-vector.xml\", 0);\n }\n- switch (env->misa_mxl_max) {\n+ switch (mcc->misa_mxl_max) {\n case MXL_RV32:\n gdb_register_coprocessor(cs, riscv_gdb_get_virtual,\n riscv_gdb_set_virtual,\ndiff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c\nindex 117e33cf90f..ed86f21b8f2 100644\n--- a/target/riscv/kvm/kvm-cpu.c\n+++ b/target/riscv/kvm/kvm-cpu.c\n@@ -1499,14 +1499,14 @@ static void kvm_cpu_accel_register_types(void)\n }\n type_init(kvm_cpu_accel_register_types);\n \n-static void riscv_host_cpu_init(Object *obj)\n+static void riscv_host_cpu_class_init(ObjectClass *c, void *data)\n {\n- CPURISCVState *env = &RISCV_CPU(obj)->env;\n+ RISCVCPUClass *mcc = RISCV_CPU_CLASS(c);\n \n #if defined(TARGET_RISCV32)\n- env->misa_mxl_max = env->misa_mxl = MXL_RV32;\n+ mcc->misa_mxl_max = MXL_RV32;\n #elif defined(TARGET_RISCV64)\n- env->misa_mxl_max = env->misa_mxl = MXL_RV64;\n+ mcc->misa_mxl_max = MXL_RV64;\n #endif\n }\n \n@@ -1514,7 +1514,7 @@ static const TypeInfo riscv_kvm_cpu_type_infos[] = {\n {\n .name = TYPE_RISCV_CPU_HOST,\n .parent = TYPE_RISCV_CPU,\n- .instance_init = riscv_host_cpu_init,\n+ .class_init = riscv_host_cpu_class_init,\n }\n };\n \ndiff --git a/target/riscv/machine.c b/target/riscv/machine.c\nindex fdde243e040..4c8d9a66595 100644\n--- a/target/riscv/machine.c\n+++ b/target/riscv/machine.c\n@@ -178,10 +178,9 @@ static const VMStateDescription vmstate_pointermasking = {\n \n static bool rv128_needed(void *opaque)\n {\n- RISCVCPU *cpu = opaque;\n- CPURISCVState *env = &cpu->env;\n+ RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(opaque);\n \n- return env->misa_mxl_max == MXL_RV128;\n+ return mcc->misa_mxl_max == MXL_RV128;\n }\n \n static const VMStateDescription vmstate_rv128 = {\n@@ -372,7 +371,7 @@ const VMStateDescription vmstate_riscv_cpu = {\n VMSTATE_UINTTL(env.vext_ver, RISCVCPU),\n VMSTATE_UINT32(env.misa_mxl, RISCVCPU),\n VMSTATE_UINT32(env.misa_ext, RISCVCPU),\n- VMSTATE_UINT32(env.misa_mxl_max, RISCVCPU),\n+ VMSTATE_UNUSED(4),\n VMSTATE_UINT32(env.misa_ext_mask, RISCVCPU),\n VMSTATE_UINTTL(env.priv, RISCVCPU),\n VMSTATE_BOOL(env.virt_enabled, RISCVCPU),\ndiff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c\nindex ee17f65afb6..7f6712c81a4 100644\n--- a/target/riscv/tcg/tcg-cpu.c\n+++ b/target/riscv/tcg/tcg-cpu.c\n@@ -152,10 +152,9 @@ static void riscv_cpu_validate_misa_mxl(RISCVCPU *cpu)\n {\n RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu);\n CPUClass *cc = CPU_CLASS(mcc);\n- CPURISCVState *env = &cpu->env;\n \n /* Validate that MISA_MXL is set properly. */\n- switch (env->misa_mxl_max) {\n+ switch (mcc->misa_mxl_max) {\n #ifdef TARGET_RISCV64\n case MXL_RV64:\n case MXL_RV128:\n@@ -274,6 +273,7 @@ static void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu)\n */\n void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)\n {\n+ RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu);\n CPURISCVState *env = &cpu->env;\n Error *local_err = NULL;\n \n@@ -454,7 +454,7 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)\n cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcb), true);\n cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcmp), true);\n cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcmt), true);\n- if (riscv_has_ext(env, RVF) && env->misa_mxl_max == MXL_RV32) {\n+ if (riscv_has_ext(env, RVF) && mcc->misa_mxl_max == MXL_RV32) {\n cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcf), true);\n }\n }\n@@ -462,7 +462,7 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)\n /* zca, zcd and zcf has a PRIV 1.12.0 restriction */\n if (riscv_has_ext(env, RVC) && env->priv_ver >= PRIV_VERSION_1_12_0) {\n cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zca), true);\n- if (riscv_has_ext(env, RVF) && env->misa_mxl_max == MXL_RV32) {\n+ if (riscv_has_ext(env, RVF) && mcc->misa_mxl_max == MXL_RV32) {\n cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcf), true);\n }\n if (riscv_has_ext(env, RVD)) {\n@@ -470,7 +470,7 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)\n }\n }\n \n- if (env->misa_mxl_max != MXL_RV32 && cpu->cfg.ext_zcf) {\n+ if (mcc->misa_mxl_max != MXL_RV32 && cpu->cfg.ext_zcf) {\n error_setg(errp, \"Zcf extension is only relevant to RV32\");\n return;\n }\n@@ -956,7 +956,7 @@ static void riscv_init_max_cpu_extensions(Object *obj)\n const RISCVCPUMultiExtConfig *prop;\n \n /* Enable RVG, RVJ and RVV that are disabled by default */\n- riscv_cpu_set_misa(env, env->misa_mxl, env->misa_ext | RVG | RVJ | RVV);\n+ riscv_cpu_set_misa_ext(env, env->misa_ext | RVG | RVJ | RVV);\n \n for (prop = riscv_cpu_extensions; prop && prop->name; prop++) {\n isa_ext_update_enabled(cpu, prop->offset, true);\ndiff --git a/target/riscv/translate.c b/target/riscv/translate.c\nindex f0be79bb160..7e383c5eebf 100644\n--- a/target/riscv/translate.c\n+++ b/target/riscv/translate.c\n@@ -1167,6 +1167,7 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)\n {\n DisasContext *ctx = container_of(dcbase, DisasContext, base);\n CPURISCVState *env = cpu_env(cs);\n+ RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cs);\n RISCVCPU *cpu = RISCV_CPU(cs);\n uint32_t tb_flags = ctx->base.tb->flags;\n \n@@ -1188,7 +1189,7 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)\n ctx->cfg_vta_all_1s = cpu->cfg.rvv_ta_all_1s;\n ctx->vstart_eq_zero = FIELD_EX32(tb_flags, TB_FLAGS, VSTART_EQ_ZERO);\n ctx->vl_eq_vlmax = FIELD_EX32(tb_flags, TB_FLAGS, VL_EQ_VLMAX);\n- ctx->misa_mxl_max = env->misa_mxl_max;\n+ ctx->misa_mxl_max = mcc->misa_mxl_max;\n ctx->xl = FIELD_EX32(tb_flags, TB_FLAGS, XL);\n ctx->address_xl = FIELD_EX32(tb_flags, TB_FLAGS, AXL);\n ctx->cs = cs;\n","prefixes":["v2","24/43"]}