{"id":1882081,"url":"http://patchwork.ozlabs.org/api/patches/1882081/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20240103173349.398526-24-alex.bennee@linaro.org/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20240103173349.398526-24-alex.bennee@linaro.org>","list_archive_url":null,"date":"2024-01-03T17:33:29","name":"[v2,23/43] target/riscv: Remove misa_mxl validation","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"9ca7a821b8dd40f6dcddb847d6a752c3e304d886","submitter":{"id":39532,"url":"http://patchwork.ozlabs.org/api/people/39532/?format=json","name":"Alex Bennée","email":"alex.bennee@linaro.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20240103173349.398526-24-alex.bennee@linaro.org/mbox/","series":[{"id":388742,"url":"http://patchwork.ozlabs.org/api/series/388742/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=388742","date":"2024-01-03T17:33:08","name":"testing and plugin updates for 9.0 (pre-PR)","version":2,"mbox":"http://patchwork.ozlabs.org/series/388742/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/1882081/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/1882081/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=wCnmPOkE;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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Iglesias\" ,\n Eduardo Habkost ,\n Pierrick Bouvier , qemu-riscv@nongnu.org,\n Alistair Francis ,\n Akihiko Odaki ","Subject":"[PATCH v2 23/43] target/riscv: Remove misa_mxl validation","Date":"Wed, 3 Jan 2024 17:33:29 +0000","Message-Id":"<20240103173349.398526-24-alex.bennee@linaro.org>","X-Mailer":"git-send-email 2.39.2","In-Reply-To":"<20240103173349.398526-1-alex.bennee@linaro.org>","References":"<20240103173349.398526-1-alex.bennee@linaro.org>","MIME-Version":"1.0","Content-Type":"text/plain; charset=UTF-8","Content-Transfer-Encoding":"8bit","Received-SPF":"pass client-ip=2a00:1450:4864:20::333;\n envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x333.google.com","X-Spam_score_int":"-20","X-Spam_score":"-2.1","X-Spam_bar":"--","X-Spam_report":"(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001,\n T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"From: Akihiko Odaki \n\nIt is initialized with a simple assignment and there is little room for\nerror. In fact, the validation is even more complex.\n\nSigned-off-by: Akihiko Odaki \nAcked-by: LIU Zhiwei \nReviewed-by: Daniel Henrique Barboza \nAcked-by: Alistair Francis \nMessage-Id: <20231213-riscv-v7-2-a760156a337f@daynix.com>\nSigned-off-by: Alex Bennée \n---\n target/riscv/tcg/tcg-cpu.c | 15 +++------------\n 1 file changed, 3 insertions(+), 12 deletions(-)","diff":"diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c\nindex 8a35683a345..ee17f65afb6 100644\n--- a/target/riscv/tcg/tcg-cpu.c\n+++ b/target/riscv/tcg/tcg-cpu.c\n@@ -148,7 +148,7 @@ static void riscv_cpu_validate_misa_priv(CPURISCVState *env, Error **errp)\n }\n }\n \n-static void riscv_cpu_validate_misa_mxl(RISCVCPU *cpu, Error **errp)\n+static void riscv_cpu_validate_misa_mxl(RISCVCPU *cpu)\n {\n RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu);\n CPUClass *cc = CPU_CLASS(mcc);\n@@ -168,11 +168,6 @@ static void riscv_cpu_validate_misa_mxl(RISCVCPU *cpu, Error **errp)\n default:\n g_assert_not_reached();\n }\n-\n- if (env->misa_mxl_max != env->misa_mxl) {\n- error_setg(errp, \"misa_mxl_max must be equal to misa_mxl\");\n- return;\n- }\n }\n \n static void riscv_cpu_validate_priv_spec(RISCVCPU *cpu, Error **errp)\n@@ -673,7 +668,6 @@ static bool riscv_cpu_is_generic(Object *cpu_obj)\n static bool tcg_cpu_realize(CPUState *cs, Error **errp)\n {\n RISCVCPU *cpu = RISCV_CPU(cs);\n- Error *local_err = NULL;\n \n if (!riscv_cpu_tcg_compatible(cpu)) {\n g_autofree char *name = riscv_cpu_get_name(cpu);\n@@ -682,14 +676,11 @@ static bool tcg_cpu_realize(CPUState *cs, Error **errp)\n return false;\n }\n \n- riscv_cpu_validate_misa_mxl(cpu, &local_err);\n- if (local_err != NULL) {\n- error_propagate(errp, local_err);\n- return false;\n- }\n+ riscv_cpu_validate_misa_mxl(cpu);\n \n #ifndef CONFIG_USER_ONLY\n CPURISCVState *env = &cpu->env;\n+ Error *local_err = NULL;\n \n CPU(cs)->tcg_cflags |= CF_PCREL;\n \n","prefixes":["v2","23/43"]}