{"id":1839981,"url":"http://patchwork.ozlabs.org/api/patches/1839981/?format=json","web_url":"http://patchwork.ozlabs.org/project/gcc/patch/patch-17718-tamar@arm.com/","project":{"id":17,"url":"http://patchwork.ozlabs.org/api/projects/17/?format=json","name":"GNU Compiler Collection","link_name":"gcc","list_id":"gcc-patches.gcc.gnu.org","list_email":"gcc-patches@gcc.gnu.org","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<patch-17718-tamar@arm.com>","list_archive_url":null,"date":"2023-09-27T00:50:15","name":"middle-end match.pd: optimize fneg (fabs (x)) to x | (1 << signbit(x)) [PR109154]","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"105b9767e421315a38c5e4c8e880041ace156f08","submitter":{"id":69689,"url":"http://patchwork.ozlabs.org/api/people/69689/?format=json","name":"Tamar Christina","email":"Tamar.Christina@arm.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/gcc/patch/patch-17718-tamar@arm.com/mbox/","series":[{"id":375019,"url":"http://patchwork.ozlabs.org/api/series/375019/?format=json","web_url":"http://patchwork.ozlabs.org/project/gcc/list/?series=375019","date":"2023-09-27T00:50:15","name":"middle-end match.pd: optimize fneg (fabs (x)) to x | (1 << signbit(x)) [PR109154]","version":1,"mbox":"http://patchwork.ozlabs.org/series/375019/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/1839981/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/1839981/checks/","tags":{},"related":[],"headers":{"Return-Path":"<gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org>","X-Original-To":["incoming@patchwork.ozlabs.org","gcc-patches@gcc.gnu.org"],"Delivered-To":["patchwork-incoming@legolas.ozlabs.org","gcc-patches@gcc.gnu.org"],"Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=armh.onmicrosoft.com header.i=@armh.onmicrosoft.com\n header.a=rsa-sha256 header.s=selector2-armh-onmicrosoft-com\n header.b=QPqQAg//;\n\tdkim=pass (1024-bit key) header.d=armh.onmicrosoft.com\n header.i=@armh.onmicrosoft.com header.a=rsa-sha256\n header.s=selector2-armh-onmicrosoft-com header.b=QPqQAg//;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org\n (client-ip=2620:52:3:1:0:246e:9693:128c; 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Ip=[63.35.35.123];\n Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com]","X-MS-Exchange-CrossTenant-AuthSource":"\n DBAEUR03FT058.eop-EUR03.prod.protection.outlook.com","X-MS-Exchange-CrossTenant-AuthAs":"Anonymous","X-MS-Exchange-CrossTenant-FromEntityHeader":"HybridOnPrem","X-Spam-Status":"No, score=-12.0 required=5.0 tests=BAYES_00, DKIM_SIGNED,\n DKIM_VALID, FORGED_SPF_HELO, GIT_PATCH_0, KAM_DMARC_NONE, KAM_LOTSOFHASH,\n KAM_SHORT, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_NONE,\n TXREP, UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.6","X-Spam-Checker-Version":"SpamAssassin 3.4.6 (2021-04-09) on\n server2.sourceware.org","X-BeenThere":"gcc-patches@gcc.gnu.org","X-Mailman-Version":"2.1.30","Precedence":"list","List-Id":"Gcc-patches mailing list <gcc-patches.gcc.gnu.org>","List-Unsubscribe":"<https://gcc.gnu.org/mailman/options/gcc-patches>,\n <mailto:gcc-patches-request@gcc.gnu.org?subject=unsubscribe>","List-Archive":"<https://gcc.gnu.org/pipermail/gcc-patches/>","List-Post":"<mailto:gcc-patches@gcc.gnu.org>","List-Help":"<mailto:gcc-patches-request@gcc.gnu.org?subject=help>","List-Subscribe":"<https://gcc.gnu.org/mailman/listinfo/gcc-patches>,\n <mailto:gcc-patches-request@gcc.gnu.org?subject=subscribe>","Errors-To":"gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org"},"content":"Hi All,\n\nFor targets that allow conversion between int and float modes this adds a new\noptimization transforming fneg (fabs (x)) into x | (1 << signbit(x)).  Such\nsequences are common in scientific code working with gradients.\n\nThe transformed instruction if the target has an inclusive-OR that takes an\nimmediate is both shorter an faster.  For those that don't the immediate has\nto be seperate constructed but this still ends up being faster as the immediate\nconstruction is not on the critical path.\n\nBootstrapped Regtested on aarch64-none-linux-gnu and no issues.\n\nOk for master?\n\nThanks,\nTamar\n\ngcc/ChangeLog:\n\n\tPR tree-optimization/109154\n\t* match.pd: Add new neg+abs rule.\n\ngcc/testsuite/ChangeLog:\n\n\tPR tree-optimization/109154\n\t* gcc.target/aarch64/fneg-abs_1.c: New test.\n\t* gcc.target/aarch64/fneg-abs_2.c: New test.\n\t* gcc.target/aarch64/fneg-abs_3.c: New test.\n\t* gcc.target/aarch64/fneg-abs_4.c: New test.\n\t* gcc.target/aarch64/sve/fneg-abs_1.c: New test.\n\t* gcc.target/aarch64/sve/fneg-abs_2.c: New test.\n\t* gcc.target/aarch64/sve/fneg-abs_3.c: New test.\n\t* gcc.target/aarch64/sve/fneg-abs_4.c: New test.\n\n--- inline copy of patch -- \ndiff --git a/gcc/match.pd b/gcc/match.pd\nindex 39c7ea1088f25538ed8bd26ee89711566141a71f..8ebde06dcd4b26d694826cffad0fb17e1136600a 100644\n\n\n\n\n--\ndiff --git a/gcc/match.pd b/gcc/match.pd\nindex 39c7ea1088f25538ed8bd26ee89711566141a71f..8ebde06dcd4b26d694826cffad0fb17e1136600a 100644\n--- a/gcc/match.pd\n+++ b/gcc/match.pd\n@@ -9476,3 +9476,57 @@ and,\n       }\n       (if (full_perm_p)\n \t(vec_perm (op@3 @0 @1) @3 @2))))))\n+\n+/* Transform fneg (fabs (X)) -> X | 1 << signbit (X).  */\n+\n+(simplify\n+ (negate (abs @0))\n+ (if (FLOAT_TYPE_P (type)\n+      /* We have to delay this rewriting till after forward prop because otherwise\n+\t it's harder to do trigonometry optimizations. e.g. cos(-fabs(x)) is not\n+\t matched in one go.  Instead cos (-x) is matched first followed by cos(|x|).\n+\t The bottom op approach makes this rule match first and it's not untill\n+\t fwdprop that we match top down.  There are manu such simplications so we\n+\t delay this optimization till later on.  */\n+      && canonicalize_math_after_vectorization_p ())\n+  (with {\n+    tree itype = unsigned_type_for (type);\n+    machine_mode mode = TYPE_MODE (type);\n+    const struct real_format *float_fmt = FLOAT_MODE_FORMAT (mode);\n+    auto optab = VECTOR_TYPE_P (type) ? optab_vector : optab_default; }\n+   (if (float_fmt\n+\t&& float_fmt->signbit_rw >= 0\n+\t&& targetm.can_change_mode_class (TYPE_MODE (itype),\n+\t\t\t\t\t  TYPE_MODE (type), ALL_REGS)\n+        && target_supports_op_p (itype, BIT_IOR_EXPR, optab))\n+    (with { wide_int wone = wi::one (element_precision (type));\n+\t    int sbit = float_fmt->signbit_rw;\n+\t    auto stype = VECTOR_TYPE_P (type) ? TREE_TYPE (itype) : itype;\n+\t    tree sign_bit = wide_int_to_tree (stype, wi::lshift (wone, sbit));}\n+     (view_convert:type\n+      (bit_ior (view_convert:itype @0)\n+\t       { build_uniform_cst (itype, sign_bit); } )))))))\n+\n+/* Repeat the same but for conditional negate.  */\n+\n+(simplify\n+ (IFN_COND_NEG @1 (abs @0) @2)\n+ (if (FLOAT_TYPE_P (type))\n+  (with {\n+    tree itype = unsigned_type_for (type);\n+    machine_mode mode = TYPE_MODE (type);\n+    const struct real_format *float_fmt = FLOAT_MODE_FORMAT (mode);\n+    auto optab = VECTOR_TYPE_P (type) ? optab_vector : optab_default; }\n+   (if (float_fmt\n+\t&& float_fmt->signbit_rw >= 0\n+\t&& targetm.can_change_mode_class (TYPE_MODE (itype),\n+\t\t\t\t\t  TYPE_MODE (type), ALL_REGS)\n+        && target_supports_op_p (itype, BIT_IOR_EXPR, optab))\n+    (with { wide_int wone = wi::one (element_precision (type));\n+\t    int sbit = float_fmt->signbit_rw;\n+\t    auto stype = VECTOR_TYPE_P (type) ? TREE_TYPE (itype) : itype;\n+\t    tree sign_bit = wide_int_to_tree (stype, wi::lshift (wone, sbit));}\n+     (view_convert:type\n+      (IFN_COND_IOR @1 (view_convert:itype @0)\n+\t       { build_uniform_cst (itype, sign_bit); }\n+\t       (view_convert:itype @2) )))))))\n\\ No newline at end of file\ndiff --git a/gcc/testsuite/gcc.target/aarch64/fneg-abs_1.c b/gcc/testsuite/gcc.target/aarch64/fneg-abs_1.c\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..f823013c3ddf6b3a266c3abfcbf2642fc2a75fa6\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/aarch64/fneg-abs_1.c\n@@ -0,0 +1,39 @@\n+/* { dg-do compile } */\n+/* { dg-options \"-O3\" } */\n+/* { dg-final { check-function-bodies \"**\" \"\" \"\" { target lp64 } } } */\n+\n+#pragma GCC target \"+nosve\"\n+\n+#include <arm_neon.h>\n+\n+/*\n+** t1:\n+**\torr\tv[0-9]+.2s, #128, lsl #24\n+**\tret\n+*/\n+float32x2_t t1 (float32x2_t a)\n+{\n+  return vneg_f32 (vabs_f32 (a));\n+}\n+\n+/*\n+** t2:\n+**\torr\tv[0-9]+.4s, #128, lsl #24\n+**\tret\n+*/\n+float32x4_t t2 (float32x4_t a)\n+{\n+  return vnegq_f32 (vabsq_f32 (a));\n+}\n+\n+/*\n+** t3:\n+**\tadrp\tx0, .LC[0-9]+\n+**\tldr\tq[0-9]+, \\[x0, #:lo12:.LC0\\]\n+**\torr\tv[0-9]+.16b, v[0-9]+.16b, v[0-9]+.16b\n+**\tret\n+*/\n+float64x2_t t3 (float64x2_t a)\n+{\n+  return vnegq_f64 (vabsq_f64 (a));\n+}\ndiff --git a/gcc/testsuite/gcc.target/aarch64/fneg-abs_2.c b/gcc/testsuite/gcc.target/aarch64/fneg-abs_2.c\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..141121176b309e4b2aa413dc55271a6e3c93d5e1\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/aarch64/fneg-abs_2.c\n@@ -0,0 +1,31 @@\n+/* { dg-do compile } */\n+/* { dg-options \"-O3\" } */\n+/* { dg-final { check-function-bodies \"**\" \"\" \"\" { target lp64 } } } */\n+\n+#pragma GCC target \"+nosve\"\n+\n+#include <arm_neon.h>\n+#include <math.h>\n+\n+/*\n+** f1:\n+**\tmovi\tv[0-9]+.2s, 0x80, lsl 24\n+**\torr\tv[0-9]+.8b, v[0-9]+.8b, v[0-9]+.8b\n+**\tret\n+*/\n+float32_t f1 (float32_t a)\n+{\n+  return -fabsf (a);\n+}\n+\n+/*\n+** f2:\n+**\tmov\tx0, -9223372036854775808\n+**\tfmov\td[0-9]+, x0\n+**\torr\tv[0-9]+.8b, v[0-9]+.8b, v[0-9]+.8b\n+**\tret\n+*/\n+float64_t f2 (float64_t a)\n+{\n+  return -fabs (a);\n+}\ndiff --git a/gcc/testsuite/gcc.target/aarch64/fneg-abs_3.c b/gcc/testsuite/gcc.target/aarch64/fneg-abs_3.c\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..b4652173a95d104ddfa70c497f0627a61ea89d3b\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/aarch64/fneg-abs_3.c\n@@ -0,0 +1,36 @@\n+/* { dg-do compile } */\n+/* { dg-options \"-O3\" } */\n+/* { dg-final { check-function-bodies \"**\" \"\" \"\" { target lp64 } } } */\n+\n+#pragma GCC target \"+nosve\"\n+\n+#include <arm_neon.h>\n+#include <math.h>\n+\n+/*\n+** f1:\n+**\t...\n+**\tldr\tq[0-9]+, \\[x0\\]\n+**\torr\tv[0-9]+.4s, #128, lsl #24\n+**\tstr\tq[0-9]+, \\[x0\\], 16\n+**\t...\n+*/\n+void f1 (float32_t *a, int n)\n+{\n+  for (int i = 0; i < (n & -8); i++)\n+   a[i] = -fabsf (a[i]);\n+}\n+\n+/*\n+** f2:\n+**\t...\n+**\tldr\tq[0-9]+, \\[x0\\]\n+**\torr\tv[0-9]+.16b, v[0-9]+.16b, v[0-9]+.16b\n+**\tstr\tq[0-9]+, \\[x0\\], 16\n+**\t...\n+*/\n+void f2 (float64_t *a, int n)\n+{\n+  for (int i = 0; i < (n & -8); i++)\n+   a[i] = -fabs (a[i]);\n+}\ndiff --git a/gcc/testsuite/gcc.target/aarch64/fneg-abs_4.c b/gcc/testsuite/gcc.target/aarch64/fneg-abs_4.c\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..10879dea74462d34b26160eeb0bd54ead063166b\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/aarch64/fneg-abs_4.c\n@@ -0,0 +1,39 @@\n+/* { dg-do compile } */\n+/* { dg-options \"-O3\" } */\n+/* { dg-final { check-function-bodies \"**\" \"\" \"\" { target lp64 } } } */\n+\n+#pragma GCC target \"+nosve\"\n+\n+#include <string.h>\n+\n+/*\n+** negabs:\n+**\tmov\tx0, -9223372036854775808\n+**\tfmov\td[0-9]+, x0\n+**\torr\tv[0-9]+.8b, v[0-9]+.8b, v[0-9]+.8b\n+**\tret\n+*/\n+double negabs (double x)\n+{\n+   unsigned long long y;\n+   memcpy (&y, &x, sizeof(double));\n+   y = y | (1UL << 63);\n+   memcpy (&x, &y, sizeof(double));\n+   return x;\n+}\n+\n+/*\n+** negabsf:\n+**\tmovi\tv[0-9]+.2s, 0x80, lsl 24\n+**\torr\tv[0-9]+.8b, v[0-9]+.8b, v[0-9]+.8b\n+**\tret\n+*/\n+float negabsf (float x)\n+{\n+   unsigned int y;\n+   memcpy (&y, &x, sizeof(float));\n+   y = y | (1U << 31);\n+   memcpy (&x, &y, sizeof(float));\n+   return x;\n+}\n+\ndiff --git a/gcc/testsuite/gcc.target/aarch64/sve/fneg-abs_1.c b/gcc/testsuite/gcc.target/aarch64/sve/fneg-abs_1.c\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..0c7664e6de77a497682952653ffd417453854d52\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/aarch64/sve/fneg-abs_1.c\n@@ -0,0 +1,37 @@\n+/* { dg-do compile } */\n+/* { dg-options \"-O3\" } */\n+/* { dg-final { check-function-bodies \"**\" \"\" \"\" { target lp64 } } } */\n+\n+#include <arm_neon.h>\n+\n+/*\n+** t1:\n+**\torr\tv[0-9]+.2s, #128, lsl #24\n+**\tret\n+*/\n+float32x2_t t1 (float32x2_t a)\n+{\n+  return vneg_f32 (vabs_f32 (a));\n+}\n+\n+/*\n+** t2:\n+**\torr\tv[0-9]+.4s, #128, lsl #24\n+**\tret\n+*/\n+float32x4_t t2 (float32x4_t a)\n+{\n+  return vnegq_f32 (vabsq_f32 (a));\n+}\n+\n+/*\n+** t3:\n+**\tadrp\tx0, .LC[0-9]+\n+**\tldr\tq[0-9]+, \\[x0, #:lo12:.LC0\\]\n+**\torr\tv[0-9]+.16b, v[0-9]+.16b, v[0-9]+.16b\n+**\tret\n+*/\n+float64x2_t t3 (float64x2_t a)\n+{\n+  return vnegq_f64 (vabsq_f64 (a));\n+}\ndiff --git a/gcc/testsuite/gcc.target/aarch64/sve/fneg-abs_2.c b/gcc/testsuite/gcc.target/aarch64/sve/fneg-abs_2.c\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..a60cd31b9294af2dac69eed1c93f899bd5c78fca\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/aarch64/sve/fneg-abs_2.c\n@@ -0,0 +1,29 @@\n+/* { dg-do compile } */\n+/* { dg-options \"-O3\" } */\n+/* { dg-final { check-function-bodies \"**\" \"\" \"\" { target lp64 } } } */\n+\n+#include <arm_neon.h>\n+#include <math.h>\n+\n+/*\n+** f1:\n+**\tmovi\tv[0-9]+.2s, 0x80, lsl 24\n+**\torr\tv[0-9]+.8b, v[0-9]+.8b, v[0-9]+.8b\n+**\tret\n+*/\n+float32_t f1 (float32_t a)\n+{\n+  return -fabsf (a);\n+}\n+\n+/*\n+** f2:\n+**\tmov\tx0, -9223372036854775808\n+**\tfmov\td[0-9]+, x0\n+**\torr\tv[0-9]+.8b, v[0-9]+.8b, v[0-9]+.8b\n+**\tret\n+*/\n+float64_t f2 (float64_t a)\n+{\n+  return -fabs (a);\n+}\ndiff --git a/gcc/testsuite/gcc.target/aarch64/sve/fneg-abs_3.c b/gcc/testsuite/gcc.target/aarch64/sve/fneg-abs_3.c\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..1bf34328d8841de8e6b0a5458562a9f00e31c275\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/aarch64/sve/fneg-abs_3.c\n@@ -0,0 +1,34 @@\n+/* { dg-do compile } */\n+/* { dg-options \"-O3\" } */\n+/* { dg-final { check-function-bodies \"**\" \"\" \"\" { target lp64 } } } */\n+\n+#include <arm_neon.h>\n+#include <math.h>\n+\n+/*\n+** f1:\n+**\t...\n+**\tld1w\tz[0-9]+.s, p[0-9]+/z, \\[x0, x2, lsl 2\\]\n+**\torr\tz[0-9]+.s, z[0-9]+.s, #0x80000000\n+**\tst1w\tz[0-9]+.s, p[0-9]+, \\[x0, x2, lsl 2\\]\n+**\t...\n+*/\n+void f1 (float32_t *a, int n)\n+{\n+  for (int i = 0; i < (n & -8); i++)\n+   a[i] = -fabsf (a[i]);\n+}\n+\n+/*\n+** f2:\n+**\t...\n+**\tld1d\tz[0-9]+.d, p[0-9]+/z, \\[x0, x2, lsl 3\\]\n+**\torr\tz[0-9]+.d, z[0-9]+.d, #0x8000000000000000\n+**\tst1d\tz[0-9]+.d, p[0-9]+, \\[x0, x2, lsl 3\\]\n+**\t...\n+*/\n+void f2 (float64_t *a, int n)\n+{\n+  for (int i = 0; i < (n & -8); i++)\n+   a[i] = -fabs (a[i]);\n+}\ndiff --git a/gcc/testsuite/gcc.target/aarch64/sve/fneg-abs_4.c b/gcc/testsuite/gcc.target/aarch64/sve/fneg-abs_4.c\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..21f2a8da2a5d44e3d01f6604ca7be87e3744d494\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/aarch64/sve/fneg-abs_4.c\n@@ -0,0 +1,37 @@\n+/* { dg-do compile } */\n+/* { dg-options \"-O3\" } */\n+/* { dg-final { check-function-bodies \"**\" \"\" \"\" { target lp64 } } } */\n+\n+#include <string.h>\n+\n+/*\n+** negabs:\n+**\tmov\tx0, -9223372036854775808\n+**\tfmov\td[0-9]+, x0\n+**\torr\tv[0-9]+.8b, v[0-9]+.8b, v[0-9]+.8b\n+**\tret\n+*/\n+double negabs (double x)\n+{\n+   unsigned long long y;\n+   memcpy (&y, &x, sizeof(double));\n+   y = y | (1UL << 63);\n+   memcpy (&x, &y, sizeof(double));\n+   return x;\n+}\n+\n+/*\n+** negabsf:\n+**\tmovi\tv[0-9]+.2s, 0x80, lsl 24\n+**\torr\tv[0-9]+.8b, v[0-9]+.8b, v[0-9]+.8b\n+**\tret\n+*/\n+float negabsf (float x)\n+{\n+   unsigned int y;\n+   memcpy (&y, &x, sizeof(float));\n+   y = y | (1U << 31);\n+   memcpy (&x, &y, sizeof(float));\n+   return x;\n+}\n+","diff":"--- a/gcc/match.pd\n+++ b/gcc/match.pd\n@@ -9476,3 +9476,57 @@ and,\n       }\n       (if (full_perm_p)\n \t(vec_perm (op@3 @0 @1) @3 @2))))))\n+\n+/* Transform fneg (fabs (X)) -> X | 1 << signbit (X).  */\n+\n+(simplify\n+ (negate (abs @0))\n+ (if (FLOAT_TYPE_P (type)\n+      /* We have to delay this rewriting till after forward prop because otherwise\n+\t it's harder to do trigonometry optimizations. e.g. cos(-fabs(x)) is not\n+\t matched in one go.  Instead cos (-x) is matched first followed by cos(|x|).\n+\t The bottom op approach makes this rule match first and it's not untill\n+\t fwdprop that we match top down.  There are manu such simplications so we\n+\t delay this optimization till later on.  */\n+      && canonicalize_math_after_vectorization_p ())\n+  (with {\n+    tree itype = unsigned_type_for (type);\n+    machine_mode mode = TYPE_MODE (type);\n+    const struct real_format *float_fmt = FLOAT_MODE_FORMAT (mode);\n+    auto optab = VECTOR_TYPE_P (type) ? optab_vector : optab_default; }\n+   (if (float_fmt\n+\t&& float_fmt->signbit_rw >= 0\n+\t&& targetm.can_change_mode_class (TYPE_MODE (itype),\n+\t\t\t\t\t  TYPE_MODE (type), ALL_REGS)\n+        && target_supports_op_p (itype, BIT_IOR_EXPR, optab))\n+    (with { wide_int wone = wi::one (element_precision (type));\n+\t    int sbit = float_fmt->signbit_rw;\n+\t    auto stype = VECTOR_TYPE_P (type) ? TREE_TYPE (itype) : itype;\n+\t    tree sign_bit = wide_int_to_tree (stype, wi::lshift (wone, sbit));}\n+     (view_convert:type\n+      (bit_ior (view_convert:itype @0)\n+\t       { build_uniform_cst (itype, sign_bit); } )))))))\n+\n+/* Repeat the same but for conditional negate.  */\n+\n+(simplify\n+ (IFN_COND_NEG @1 (abs @0) @2)\n+ (if (FLOAT_TYPE_P (type))\n+  (with {\n+    tree itype = unsigned_type_for (type);\n+    machine_mode mode = TYPE_MODE (type);\n+    const struct real_format *float_fmt = FLOAT_MODE_FORMAT (mode);\n+    auto optab = VECTOR_TYPE_P (type) ? optab_vector : optab_default; }\n+   (if (float_fmt\n+\t&& float_fmt->signbit_rw >= 0\n+\t&& targetm.can_change_mode_class (TYPE_MODE (itype),\n+\t\t\t\t\t  TYPE_MODE (type), ALL_REGS)\n+        && target_supports_op_p (itype, BIT_IOR_EXPR, optab))\n+    (with { wide_int wone = wi::one (element_precision (type));\n+\t    int sbit = float_fmt->signbit_rw;\n+\t    auto stype = VECTOR_TYPE_P (type) ? TREE_TYPE (itype) : itype;\n+\t    tree sign_bit = wide_int_to_tree (stype, wi::lshift (wone, sbit));}\n+     (view_convert:type\n+      (IFN_COND_IOR @1 (view_convert:itype @0)\n+\t       { build_uniform_cst (itype, sign_bit); }\n+\t       (view_convert:itype @2) )))))))\n\\ No newline at end of file\ndiff --git a/gcc/testsuite/gcc.target/aarch64/fneg-abs_1.c b/gcc/testsuite/gcc.target/aarch64/fneg-abs_1.c\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..f823013c3ddf6b3a266c3abfcbf2642fc2a75fa6\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/aarch64/fneg-abs_1.c\n@@ -0,0 +1,39 @@\n+/* { dg-do compile } */\n+/* { dg-options \"-O3\" } */\n+/* { dg-final { check-function-bodies \"**\" \"\" \"\" { target lp64 } } } */\n+\n+#pragma GCC target \"+nosve\"\n+\n+#include <arm_neon.h>\n+\n+/*\n+** t1:\n+**\torr\tv[0-9]+.2s, #128, lsl #24\n+**\tret\n+*/\n+float32x2_t t1 (float32x2_t a)\n+{\n+  return vneg_f32 (vabs_f32 (a));\n+}\n+\n+/*\n+** t2:\n+**\torr\tv[0-9]+.4s, #128, lsl #24\n+**\tret\n+*/\n+float32x4_t t2 (float32x4_t a)\n+{\n+  return vnegq_f32 (vabsq_f32 (a));\n+}\n+\n+/*\n+** t3:\n+**\tadrp\tx0, .LC[0-9]+\n+**\tldr\tq[0-9]+, \\[x0, #:lo12:.LC0\\]\n+**\torr\tv[0-9]+.16b, v[0-9]+.16b, v[0-9]+.16b\n+**\tret\n+*/\n+float64x2_t t3 (float64x2_t a)\n+{\n+  return vnegq_f64 (vabsq_f64 (a));\n+}\ndiff --git a/gcc/testsuite/gcc.target/aarch64/fneg-abs_2.c b/gcc/testsuite/gcc.target/aarch64/fneg-abs_2.c\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..141121176b309e4b2aa413dc55271a6e3c93d5e1\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/aarch64/fneg-abs_2.c\n@@ -0,0 +1,31 @@\n+/* { dg-do compile } */\n+/* { dg-options \"-O3\" } */\n+/* { dg-final { check-function-bodies \"**\" \"\" \"\" { target lp64 } } } */\n+\n+#pragma GCC target \"+nosve\"\n+\n+#include <arm_neon.h>\n+#include <math.h>\n+\n+/*\n+** f1:\n+**\tmovi\tv[0-9]+.2s, 0x80, lsl 24\n+**\torr\tv[0-9]+.8b, v[0-9]+.8b, v[0-9]+.8b\n+**\tret\n+*/\n+float32_t f1 (float32_t a)\n+{\n+  return -fabsf (a);\n+}\n+\n+/*\n+** f2:\n+**\tmov\tx0, -9223372036854775808\n+**\tfmov\td[0-9]+, x0\n+**\torr\tv[0-9]+.8b, v[0-9]+.8b, v[0-9]+.8b\n+**\tret\n+*/\n+float64_t f2 (float64_t a)\n+{\n+  return -fabs (a);\n+}\ndiff --git a/gcc/testsuite/gcc.target/aarch64/fneg-abs_3.c b/gcc/testsuite/gcc.target/aarch64/fneg-abs_3.c\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..b4652173a95d104ddfa70c497f0627a61ea89d3b\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/aarch64/fneg-abs_3.c\n@@ -0,0 +1,36 @@\n+/* { dg-do compile } */\n+/* { dg-options \"-O3\" } */\n+/* { dg-final { check-function-bodies \"**\" \"\" \"\" { target lp64 } } } */\n+\n+#pragma GCC target \"+nosve\"\n+\n+#include <arm_neon.h>\n+#include <math.h>\n+\n+/*\n+** f1:\n+**\t...\n+**\tldr\tq[0-9]+, \\[x0\\]\n+**\torr\tv[0-9]+.4s, #128, lsl #24\n+**\tstr\tq[0-9]+, \\[x0\\], 16\n+**\t...\n+*/\n+void f1 (float32_t *a, int n)\n+{\n+  for (int i = 0; i < (n & -8); i++)\n+   a[i] = -fabsf (a[i]);\n+}\n+\n+/*\n+** f2:\n+**\t...\n+**\tldr\tq[0-9]+, \\[x0\\]\n+**\torr\tv[0-9]+.16b, v[0-9]+.16b, v[0-9]+.16b\n+**\tstr\tq[0-9]+, \\[x0\\], 16\n+**\t...\n+*/\n+void f2 (float64_t *a, int n)\n+{\n+  for (int i = 0; i < (n & -8); i++)\n+   a[i] = -fabs (a[i]);\n+}\ndiff --git a/gcc/testsuite/gcc.target/aarch64/fneg-abs_4.c b/gcc/testsuite/gcc.target/aarch64/fneg-abs_4.c\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..10879dea74462d34b26160eeb0bd54ead063166b\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/aarch64/fneg-abs_4.c\n@@ -0,0 +1,39 @@\n+/* { dg-do compile } */\n+/* { dg-options \"-O3\" } */\n+/* { dg-final { check-function-bodies \"**\" \"\" \"\" { target lp64 } } } */\n+\n+#pragma GCC target \"+nosve\"\n+\n+#include <string.h>\n+\n+/*\n+** negabs:\n+**\tmov\tx0, -9223372036854775808\n+**\tfmov\td[0-9]+, x0\n+**\torr\tv[0-9]+.8b, v[0-9]+.8b, v[0-9]+.8b\n+**\tret\n+*/\n+double negabs (double x)\n+{\n+   unsigned long long y;\n+   memcpy (&y, &x, sizeof(double));\n+   y = y | (1UL << 63);\n+   memcpy (&x, &y, sizeof(double));\n+   return x;\n+}\n+\n+/*\n+** negabsf:\n+**\tmovi\tv[0-9]+.2s, 0x80, lsl 24\n+**\torr\tv[0-9]+.8b, v[0-9]+.8b, v[0-9]+.8b\n+**\tret\n+*/\n+float negabsf (float x)\n+{\n+   unsigned int y;\n+   memcpy (&y, &x, sizeof(float));\n+   y = y | (1U << 31);\n+   memcpy (&x, &y, sizeof(float));\n+   return x;\n+}\n+\ndiff --git a/gcc/testsuite/gcc.target/aarch64/sve/fneg-abs_1.c b/gcc/testsuite/gcc.target/aarch64/sve/fneg-abs_1.c\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..0c7664e6de77a497682952653ffd417453854d52\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/aarch64/sve/fneg-abs_1.c\n@@ -0,0 +1,37 @@\n+/* { dg-do compile } */\n+/* { dg-options \"-O3\" } */\n+/* { dg-final { check-function-bodies \"**\" \"\" \"\" { target lp64 } } } */\n+\n+#include <arm_neon.h>\n+\n+/*\n+** t1:\n+**\torr\tv[0-9]+.2s, #128, lsl #24\n+**\tret\n+*/\n+float32x2_t t1 (float32x2_t a)\n+{\n+  return vneg_f32 (vabs_f32 (a));\n+}\n+\n+/*\n+** t2:\n+**\torr\tv[0-9]+.4s, #128, lsl #24\n+**\tret\n+*/\n+float32x4_t t2 (float32x4_t a)\n+{\n+  return vnegq_f32 (vabsq_f32 (a));\n+}\n+\n+/*\n+** t3:\n+**\tadrp\tx0, .LC[0-9]+\n+**\tldr\tq[0-9]+, \\[x0, #:lo12:.LC0\\]\n+**\torr\tv[0-9]+.16b, v[0-9]+.16b, v[0-9]+.16b\n+**\tret\n+*/\n+float64x2_t t3 (float64x2_t a)\n+{\n+  return vnegq_f64 (vabsq_f64 (a));\n+}\ndiff --git a/gcc/testsuite/gcc.target/aarch64/sve/fneg-abs_2.c b/gcc/testsuite/gcc.target/aarch64/sve/fneg-abs_2.c\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..a60cd31b9294af2dac69eed1c93f899bd5c78fca\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/aarch64/sve/fneg-abs_2.c\n@@ -0,0 +1,29 @@\n+/* { dg-do compile } */\n+/* { dg-options \"-O3\" } */\n+/* { dg-final { check-function-bodies \"**\" \"\" \"\" { target lp64 } } } */\n+\n+#include <arm_neon.h>\n+#include <math.h>\n+\n+/*\n+** f1:\n+**\tmovi\tv[0-9]+.2s, 0x80, lsl 24\n+**\torr\tv[0-9]+.8b, v[0-9]+.8b, v[0-9]+.8b\n+**\tret\n+*/\n+float32_t f1 (float32_t a)\n+{\n+  return -fabsf (a);\n+}\n+\n+/*\n+** f2:\n+**\tmov\tx0, -9223372036854775808\n+**\tfmov\td[0-9]+, x0\n+**\torr\tv[0-9]+.8b, v[0-9]+.8b, v[0-9]+.8b\n+**\tret\n+*/\n+float64_t f2 (float64_t a)\n+{\n+  return -fabs (a);\n+}\ndiff --git a/gcc/testsuite/gcc.target/aarch64/sve/fneg-abs_3.c b/gcc/testsuite/gcc.target/aarch64/sve/fneg-abs_3.c\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..1bf34328d8841de8e6b0a5458562a9f00e31c275\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/aarch64/sve/fneg-abs_3.c\n@@ -0,0 +1,34 @@\n+/* { dg-do compile } */\n+/* { dg-options \"-O3\" } */\n+/* { dg-final { check-function-bodies \"**\" \"\" \"\" { target lp64 } } } */\n+\n+#include <arm_neon.h>\n+#include <math.h>\n+\n+/*\n+** f1:\n+**\t...\n+**\tld1w\tz[0-9]+.s, p[0-9]+/z, \\[x0, x2, lsl 2\\]\n+**\torr\tz[0-9]+.s, z[0-9]+.s, #0x80000000\n+**\tst1w\tz[0-9]+.s, p[0-9]+, \\[x0, x2, lsl 2\\]\n+**\t...\n+*/\n+void f1 (float32_t *a, int n)\n+{\n+  for (int i = 0; i < (n & -8); i++)\n+   a[i] = -fabsf (a[i]);\n+}\n+\n+/*\n+** f2:\n+**\t...\n+**\tld1d\tz[0-9]+.d, p[0-9]+/z, \\[x0, x2, lsl 3\\]\n+**\torr\tz[0-9]+.d, z[0-9]+.d, #0x8000000000000000\n+**\tst1d\tz[0-9]+.d, p[0-9]+, \\[x0, x2, lsl 3\\]\n+**\t...\n+*/\n+void f2 (float64_t *a, int n)\n+{\n+  for (int i = 0; i < (n & -8); i++)\n+   a[i] = -fabs (a[i]);\n+}\ndiff --git a/gcc/testsuite/gcc.target/aarch64/sve/fneg-abs_4.c b/gcc/testsuite/gcc.target/aarch64/sve/fneg-abs_4.c\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..21f2a8da2a5d44e3d01f6604ca7be87e3744d494\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/aarch64/sve/fneg-abs_4.c\n@@ -0,0 +1,37 @@\n+/* { dg-do compile } */\n+/* { dg-options \"-O3\" } */\n+/* { dg-final { check-function-bodies \"**\" \"\" \"\" { target lp64 } } } */\n+\n+#include <string.h>\n+\n+/*\n+** negabs:\n+**\tmov\tx0, -9223372036854775808\n+**\tfmov\td[0-9]+, x0\n+**\torr\tv[0-9]+.8b, v[0-9]+.8b, v[0-9]+.8b\n+**\tret\n+*/\n+double negabs (double x)\n+{\n+   unsigned long long y;\n+   memcpy (&y, &x, sizeof(double));\n+   y = y | (1UL << 63);\n+   memcpy (&x, &y, sizeof(double));\n+   return x;\n+}\n+\n+/*\n+** negabsf:\n+**\tmovi\tv[0-9]+.2s, 0x80, lsl 24\n+**\torr\tv[0-9]+.8b, v[0-9]+.8b, v[0-9]+.8b\n+**\tret\n+*/\n+float negabsf (float x)\n+{\n+   unsigned int y;\n+   memcpy (&y, &x, sizeof(float));\n+   y = y | (1U << 31);\n+   memcpy (&x, &y, sizeof(float));\n+   return x;\n+}\n+\n","prefixes":[]}