{"id":1839927,"url":"http://patchwork.ozlabs.org/api/patches/1839927/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20230926194951.183767-5-dbarboza@ventanamicro.com/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20230926194951.183767-5-dbarboza@ventanamicro.com>","list_archive_url":null,"date":"2023-09-26T19:49:48","name":"[4/6] target/riscv/tcg: implement rva22u64 profile","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"c60ece7242fa229a876621a913d76d9850ebafa5","submitter":{"id":85468,"url":"http://patchwork.ozlabs.org/api/people/85468/?format=json","name":"Daniel Henrique Barboza","email":"dbarboza@ventanamicro.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20230926194951.183767-5-dbarboza@ventanamicro.com/mbox/","series":[{"id":374996,"url":"http://patchwork.ozlabs.org/api/series/374996/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=374996","date":"2023-09-26T19:49:50","name":"riscv: RVA22U64 profile support","version":1,"mbox":"http://patchwork.ozlabs.org/series/374996/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/1839927/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/1839927/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=ventanamicro.com header.i=@ventanamicro.com\n header.a=rsa-sha256 header.s=google header.b=ojvBEWwd;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from lists.gnu.org (lists.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4Rw9NB1H7nz1yqV\n\tfor ; Wed, 27 Sep 2023 05:51:06 +1000 (AEST)","from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from )\n\tid 1qlE4k-0003v9-R1; Tue, 26 Sep 2023 15:50:30 -0400","from eggs.gnu.org ([2001:470:142:3::10])\n by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from )\n id 1qlE4V-0003sW-Ue\n for qemu-devel@nongnu.org; Tue, 26 Sep 2023 15:50:17 -0400","from mail-pl1-x630.google.com ([2607:f8b0:4864:20::630])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from )\n id 1qlE4R-0001XY-C8\n for qemu-devel@nongnu.org; Tue, 26 Sep 2023 15:50:15 -0400","by mail-pl1-x630.google.com with SMTP id\n d9443c01a7336-1c3bd829b86so74625765ad.0\n for ; Tue, 26 Sep 2023 12:50:10 -0700 (PDT)","from grind.. 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The mandatory extensions\nwill be enabled via the profile flag. We'll leave the optional\nextensions to be enabled by hand.\n\nGiven that this is the first profile we're implementing in TCG we'll\nneed some wiring first. 'cpu_set_profile', our set() callback for the\nprofile user flag that we'll expose, will do the heavy lifting. We'll\nassign misa_ext and misa_ext_mask based on the profile .misa_ext, and\nenable all extensions from .ext_offsets[].\n\nWe'll also update the user choice hash 'multi_ext_user_opts' for each\nextension. The idea is to reflect that setting a profile is the same as\nsetting all extensions of the profile in the command line. This will\nprevent us from mishandling those by accident during realize() time, in\nparticular in validate_set_extensions(), when we might enable/disable\nextensions based on certain criterias.\n\nAfter cpu_set_profile() is figured out then it's a matter of exposing\nthe user flag for the profile using the profile name (in this case,\n'rva22u64') during riscv_cpu_add_user_properties().\n\nWe will expose the profile option for vendor CPUs in the next patch\nsince it requires special handling. Expose it to generic CPUs only for\nnow.\n\nHere's an example with the 'rv64' CPU:\n\n $ qemu-system-riscv64 -M virt -cpu rv64,rva22u64=true (...)\n\n # cat /proc/cpuinfo\nprocessor\t: 0\nhart\t\t: 0\nisa\t\t: rv64imafdch_zicbom_zicboz_zicntr_zicsr_zifencei_zihintntl_zihintpause_zihpm_zawrs_zfa_zfhmin_zca_zcd_zba_zbb_zbc_zbs_zkt_sstc_svadu\n\nSigned-off-by: Daniel Henrique Barboza \n---\n target/riscv/tcg/tcg-cpu.c | 55 ++++++++++++++++++++++++++++++++++++++\n 1 file changed, 55 insertions(+)","diff":"diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c\nindex 11e34782b9..03435521c9 100644\n--- a/target/riscv/tcg/tcg-cpu.c\n+++ b/target/riscv/tcg/tcg-cpu.c\n@@ -740,6 +740,57 @@ static void riscv_cpu_add_misa_properties(Object *cpu_obj)\n }\n }\n \n+static void cpu_set_profile(Object *obj, Visitor *v, const char *name,\n+ void *opaque, Error **errp)\n+{\n+ const RISCVCPUProfile *profile = opaque;\n+ RISCVCPU *cpu = RISCV_CPU(obj);\n+ CPURISCVState *env = &cpu->env;\n+ int i = 0;\n+ bool value;\n+\n+ if (!visit_type_bool(v, name, &value, errp)) {\n+ return;\n+ }\n+\n+ /* We won't disable extensions if the user disables the profile */\n+ if (!value) {\n+ return;\n+ }\n+\n+ env->misa_ext |= profile->misa_ext;\n+ env->misa_ext_mask |= profile->misa_ext;\n+\n+ for (i = 0;; i++) {\n+ int ext_offset = profile->ext_offsets[i];\n+\n+ if (ext_offset == RISCV_PROFILE_EXT_LIST_END) {\n+ break;\n+ }\n+\n+ isa_ext_update_enabled(cpu, ext_offset, true);\n+ g_hash_table_insert(multi_ext_user_opts,\n+ GUINT_TO_POINTER(ext_offset),\n+ (gpointer)true);\n+ }\n+}\n+\n+static void cpu_get_profile(Object *obj, Visitor *v, const char *name,\n+ void *opaque, Error **errp)\n+{\n+ bool value;\n+\n+ visit_type_bool(v, name, &value, errp);\n+}\n+\n+static void riscv_cpu_add_profile_prop(Object *cpu_obj,\n+ const RISCVCPUProfile *profile)\n+{\n+ object_property_add(cpu_obj, profile->name, \"bool\",\n+ cpu_get_profile, cpu_set_profile,\n+ NULL, (void *)profile);\n+}\n+\n static void cpu_set_multi_ext_cfg(Object *obj, Visitor *v, const char *name,\n void *opaque, Error **errp)\n {\n@@ -834,6 +885,10 @@ static void riscv_cpu_add_user_properties(Object *obj)\n riscv_cpu_add_multiext_prop_array(obj, riscv_cpu_vendor_exts);\n riscv_cpu_add_multiext_prop_array(obj, riscv_cpu_experimental_exts);\n \n+ if (object_dynamic_cast(obj, TYPE_RISCV_DYNAMIC_CPU) != NULL) {\n+ riscv_cpu_add_profile_prop(obj, &RVA22U64);\n+ }\n+\n for (Property *prop = riscv_cpu_options; prop && prop->name; prop++) {\n qdev_property_add_static(DEVICE(obj), prop);\n }\n","prefixes":["4/6"]}