{"id":1633406,"url":"http://patchwork.ozlabs.org/api/patches/1633406/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/patch/20220519175614.v2.1.Ieec76f320c9cc6885d7b519dffddff9ad4c97b59@changeid/","project":{"id":18,"url":"http://patchwork.ozlabs.org/api/projects/18/?format=json","name":"U-Boot","link_name":"uboot","list_id":"u-boot.lists.denx.de","list_email":"u-boot@lists.denx.de","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20220519175614.v2.1.Ieec76f320c9cc6885d7b519dffddff9ad4c97b59@changeid>","list_archive_url":null,"date":"2022-05-19T15:56:45","name":"[v2,1/3] clk: Add directory for STM32 clock drivers","commit_ref":null,"pull_url":null,"state":"superseded","archived":false,"hash":"bcc2f4c77ec93303b768abb7327da73a86d36880","submitter":{"id":80737,"url":"http://patchwork.ozlabs.org/api/people/80737/?format=json","name":"Patrick DELAUNAY","email":"patrick.delaunay@foss.st.com"},"delegate":{"id":70413,"url":"http://patchwork.ozlabs.org/api/users/70413/?format=json","username":"pchotard","first_name":"Patrice","last_name":"Chotard","email":"patrice.chotard@st.com"},"mbox":"http://patchwork.ozlabs.org/project/uboot/patch/20220519175614.v2.1.Ieec76f320c9cc6885d7b519dffddff9ad4c97b59@changeid/mbox/","series":[{"id":301147,"url":"http://patchwork.ozlabs.org/api/series/301147/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/list/?series=301147","date":"2022-05-19T15:56:46","name":"stm32mp: prepare RCC support for STM32MP13","version":2,"mbox":"http://patchwork.ozlabs.org/series/301147/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/1633406/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/1633406/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["bilbo.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=foss.st.com header.i=@foss.st.com header.a=rsa-sha256\n header.s=selector1 header.b=XiULu3Nr;\n\tdkim-atps=neutral","ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; 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Thu, 19 May\n 2022 17:56:53 +0200"],"X-Spam-Checker-Version":"SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de","X-Spam-Level":"","X-Spam-Status":"No, score=-2.0 required=5.0 tests=BAYES_00,DKIM_SIGNED,\n DKIM_VALID,DKIM_VALID_AU,SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE\n autolearn=ham autolearn_force=no version=3.4.2","DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-transfer-encoding : content-type; s=selector1;\n bh=k2XPqQP0an7xhDTzru4jRRYldHZeFuZX+mF9MA/2ZyA=;\n b=XiULu3NrgWifcKoQ6S6A9Aq+8QgykDRX8WylltsXHS+vem4yl2L3s8zzjyUeMHvcoJ9P\n tp00pW9S6+WJcg0xokjmixsS6kkuziv8qLmCiA6pIuI7zEv5qCQNaCMYvbLw6R5ZSSKV\n xnVtSYHMqqId0zbXhlUd70neFcQQBiw/9pHCdiANvK9IwrjSYrncNEfV8clUP4zs4/D0\n xzis5CAz3iHWb3+V6W/1KDxLpdziuBy1ib69sP5WevQm017gOV9IU5BeGF+d1DX8auXi\n DQFr86QImXFtNKJoEXgLNg9C36EwzYFa6EqeEdNMSQ9g9i+Zlfz+J7r/nXB9kjg5NIrO iQ==","From":"Patrick Delaunay ","To":"","CC":"Gabriel FERNANDEZ , Patrick Delaunay\n , Lukasz Majewski , Patrice\n Chotard , Sean Anderson ,\n ","Subject":"[PATCH v2 1/3] clk: Add directory for STM32 clock drivers","Date":"Thu, 19 May 2022 17:56:45 +0200","Message-ID":"\n <20220519175614.v2.1.Ieec76f320c9cc6885d7b519dffddff9ad4c97b59@changeid>","X-Mailer":"git-send-email 2.25.1","In-Reply-To":"<20220519155647.1433652-1-patrick.delaunay@foss.st.com>","References":"<20220519155647.1433652-1-patrick.delaunay@foss.st.com>","MIME-Version":"1.0","Content-Transfer-Encoding":"8bit","Content-Type":"text/plain","X-Originating-IP":"[10.75.127.50]","X-ClientProxiedBy":"SFHDAG2NODE3.st.com (10.75.127.6) To EQNDAG1NODE6.st.com\n (10.75.129.135)","X-Proofpoint-Virus-Version":"vendor=baseguard\n engine=ICAP:2.0.205,Aquarius:18.0.874,Hydra:6.0.486,FMLib:17.11.64.514\n definitions=2022-05-19_05,2022-05-19_03,2022-02-23_01","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.39","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" ","X-Virus-Scanned":"clamav-milter 0.103.5 at phobos.denx.de","X-Virus-Status":"Clean"},"content":"Add a directory in drivers/clk to regroup the clock drivers for all\nSTM32 Soc with CONFIG_ARCH_STM32 (MCUs with cortex M) or\nCONFIG_ARCH_STM32MP (MPUs with cortex A).\n\nSigned-off-by: Patrick Delaunay \n---\n\nChanges in v2:\n- replace '_' by '-' in file names to be consistant with other clk drivers\n and prepare introduction of new files for stm32mp13\n\n MAINTAINERS | 2 +-\n drivers/clk/Kconfig | 17 +-------------\n drivers/clk/Makefile | 5 ++--\n drivers/clk/stm32/Kconfig | 23 +++++++++++++++++++\n drivers/clk/stm32/Makefile | 7 ++++++\n .../clk/{clk_stm32f.c => stm32/clk-stm32f.c} | 0\n .../{clk_stm32h7.c => stm32/clk-stm32h7.c} | 0\n .../{clk_stm32mp1.c => stm32/clk-stm32mp1.c} | 0\n 8 files changed, 34 insertions(+), 20 deletions(-)\n create mode 100644 drivers/clk/stm32/Kconfig\n create mode 100644 drivers/clk/stm32/Makefile\n rename drivers/clk/{clk_stm32f.c => stm32/clk-stm32f.c} (100%)\n rename drivers/clk/{clk_stm32h7.c => stm32/clk-stm32h7.c} (100%)\n rename drivers/clk/{clk_stm32mp1.c => stm32/clk-stm32mp1.c} (100%)","diff":"diff --git a/MAINTAINERS b/MAINTAINERS\nindex 56be0bfad0..3f37edd716 100644\n--- a/MAINTAINERS\n+++ b/MAINTAINERS\n@@ -469,7 +469,7 @@ S:\tMaintained\n F:\tarch/arm/mach-stm32mp/\n F:\tdoc/board/st/\n F:\tdrivers/adc/stm32-adc*\n-F:\tdrivers/clk/clk_stm32mp1.c\n+F:\tdrivers/clk/stm32/\n F:\tdrivers/gpio/stm32_gpio.c\n F:\tdrivers/hwspinlock/stm32_hwspinlock.c\n F:\tdrivers/i2c/stm32f7_i2c.c\ndiff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig\nindex a62b81a123..fd9e1a80c6 100644\n--- a/drivers/clk/Kconfig\n+++ b/drivers/clk/Kconfig\n@@ -166,22 +166,6 @@ config CLK_SCMI\n \t by a SCMI agent based on SCMI clock protocol communication\n \t with a SCMI server.\n \n-config CLK_STM32F\n-\tbool \"Enable clock driver support for STM32F family\"\n-\tdepends on CLK && (STM32F7 || STM32F4)\n-\tdefault y\n-\thelp\n-\t This clock driver adds support for RCC clock management\n-\t for STM32F4 and STM32F7 SoCs.\n-\n-config CLK_STM32MP1\n-\tbool \"Enable RCC clock driver for STM32MP1\"\n-\tdepends on ARCH_STM32MP && CLK\n-\tdefault y\n-\thelp\n-\t Enable the STM32 clock (RCC) driver. Enable support for\n-\t manipulating STM32MP1's on-SoC clocks.\n-\n config CLK_HSDK\n \tbool \"Enable cgu clock driver for HSDK boards\"\n \tdepends on CLK && TARGET_HSDK\n@@ -251,6 +235,7 @@ source \"drivers/clk/owl/Kconfig\"\n source \"drivers/clk/renesas/Kconfig\"\n source \"drivers/clk/sunxi/Kconfig\"\n source \"drivers/clk/sifive/Kconfig\"\n+source \"drivers/clk/stm32/Kconfig\"\n source \"drivers/clk/tegra/Kconfig\"\n source \"drivers/clk/ti/Kconfig\"\n source \"drivers/clk/uniphier/Kconfig\"\ndiff --git a/drivers/clk/Makefile b/drivers/clk/Makefile\nindex f5b553172c..c274cda77c 100644\n--- a/drivers/clk/Makefile\n+++ b/drivers/clk/Makefile\n@@ -23,6 +23,8 @@ obj-$(CONFIG_ARCH_MTMIPS) += mtmips/\n obj-$(CONFIG_ARCH_NPCM) += nuvoton/\n obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/\n obj-$(CONFIG_ARCH_SOCFPGA) += altera/\n+obj-$(CONFIG_ARCH_STM32) += stm32/\n+obj-$(CONFIG_ARCH_STM32MP) += stm32/\n obj-$(CONFIG_ARCH_SUNXI) += sunxi/\n obj-$(CONFIG_CLK_AT91) += at91/\n obj-$(CONFIG_CLK_BCM6345) += clk_bcm6345.o\n@@ -39,8 +41,6 @@ obj-$(CONFIG_CLK_OWL) += owl/\n obj-$(CONFIG_CLK_RENESAS) += renesas/\n obj-$(CONFIG_CLK_SCMI) += clk_scmi.o\n obj-$(CONFIG_CLK_SIFIVE) += sifive/\n-obj-$(CONFIG_CLK_STM32F) += clk_stm32f.o\n-obj-$(CONFIG_CLK_STM32MP1) += clk_stm32mp1.o\n obj-$(CONFIG_CLK_UNIPHIER) += uniphier/\n obj-$(CONFIG_CLK_VERSACLOCK) += clk_versaclock.o\n obj-$(CONFIG_CLK_VERSAL) += clk_versal.o\n@@ -53,4 +53,3 @@ obj-$(CONFIG_MACH_PIC32) += clk_pic32.o\n obj-$(CONFIG_SANDBOX_CLK_CCF) += clk_sandbox_ccf.o\n obj-$(CONFIG_SANDBOX) += clk_sandbox.o\n obj-$(CONFIG_SANDBOX) += clk_sandbox_test.o\n-obj-$(CONFIG_STM32H7) += clk_stm32h7.o\ndiff --git a/drivers/clk/stm32/Kconfig b/drivers/clk/stm32/Kconfig\nnew file mode 100644\nindex 0000000000..eac3fc1e9d\n--- /dev/null\n+++ b/drivers/clk/stm32/Kconfig\n@@ -0,0 +1,23 @@\n+config CLK_STM32F\n+\tbool \"Enable clock driver support for STM32F family\"\n+\tdepends on CLK && (STM32F7 || STM32F4)\n+\tdefault y\n+\thelp\n+\t This clock driver adds support for RCC clock management\n+\t for STM32F4 and STM32F7 SoCs.\n+\n+config CLK_STM32H7\n+\tbool \"Enable clock driver support for STM32H7 family\"\n+\tdepends on CLK && STM32H7\n+\tdefault y\n+\thelp\n+\t This clock driver adds support for RCC clock management\n+\t for STM32H7 SoCs.\n+\n+config CLK_STM32MP1\n+\tbool \"Enable RCC clock driver for STM32MP15\"\n+\tdepends on ARCH_STM32MP && CLK\n+\tdefault y if STM32MP15x\n+\thelp\n+\t Enable the STM32 clock (RCC) driver. Enable support for\n+\t manipulating STM32MP15's on-SoC clocks.\ndiff --git a/drivers/clk/stm32/Makefile b/drivers/clk/stm32/Makefile\nnew file mode 100644\nindex 0000000000..f66f295403\n--- /dev/null\n+++ b/drivers/clk/stm32/Makefile\n@@ -0,0 +1,7 @@\n+# SPDX-License-Identifier: GPL-2.0-or-later\n+#\n+# Copyright (C) 2022, STMicroelectronics - All Rights Reserved\n+\n+obj-$(CONFIG_CLK_STM32F) += clk-stm32f.o\n+obj-$(CONFIG_CLK_STM32H7) += clk-stm32h7.o\n+obj-$(CONFIG_CLK_STM32MP1) += clk-stm32mp1.o\ndiff --git a/drivers/clk/clk_stm32f.c b/drivers/clk/stm32/clk-stm32f.c\nsimilarity index 100%\nrename from drivers/clk/clk_stm32f.c\nrename to drivers/clk/stm32/clk-stm32f.c\ndiff --git a/drivers/clk/clk_stm32h7.c b/drivers/clk/stm32/clk-stm32h7.c\nsimilarity index 100%\nrename from drivers/clk/clk_stm32h7.c\nrename to drivers/clk/stm32/clk-stm32h7.c\ndiff --git a/drivers/clk/clk_stm32mp1.c b/drivers/clk/stm32/clk-stm32mp1.c\nsimilarity index 100%\nrename from drivers/clk/clk_stm32mp1.c\nrename to drivers/clk/stm32/clk-stm32mp1.c\n","prefixes":["v2","1/3"]}