{"id":1585806,"url":"http://patchwork.ozlabs.org/api/patches/1585806/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20220128153009.2467560-6-peter.maydell@linaro.org/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20220128153009.2467560-6-peter.maydell@linaro.org>","list_archive_url":null,"date":"2022-01-28T15:29:42","name":"[PULL,05/32] hw/misc: Add a model of Versal's PMC SLCR","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"24e5c41a6f997cef4ceb4f6a88c45037ef732533","submitter":{"id":5111,"url":"http://patchwork.ozlabs.org/api/people/5111/?format=json","name":"Peter Maydell","email":"peter.maydell@linaro.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20220128153009.2467560-6-peter.maydell@linaro.org/mbox/","series":[{"id":283405,"url":"http://patchwork.ozlabs.org/api/series/283405/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=283405","date":"2022-01-28T15:29:53","name":"[PULL,01/32] Update copyright dates to 2022","version":1,"mbox":"http://patchwork.ozlabs.org/series/283405/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/1585806/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/1585806/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["bilbo.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=ZG55EGjY;\n\tdkim-atps=neutral","ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=)"],"Received":["from lists.gnu.org (lists.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby bilbo.ozlabs.org (Postfix) with ESMTPS id 4Jlk2Q58qSz9t3b\n\tfor ; Sat, 29 Jan 2022 03:49:34 +1100 (AEDT)","from localhost ([::1]:60416 helo=lists1p.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from )\n\tid 1nDURI-0007ec-15\n\tfor incoming@patchwork.ozlabs.org; Fri, 28 Jan 2022 11:49:32 -0500","from eggs.gnu.org ([209.51.188.92]:58124)\n by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from )\n id 1nDTDP-0002IS-LY\n for qemu-devel@nongnu.org; Fri, 28 Jan 2022 10:31:07 -0500","from [2a00:1450:4864:20::336] (port=41517\n helo=mail-wm1-x336.google.com)\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from )\n id 1nDTDJ-0006Lo-Bs\n for qemu-devel@nongnu.org; Fri, 28 Jan 2022 10:31:07 -0500","by mail-wm1-x336.google.com with SMTP id\n q141-20020a1ca793000000b00347b48dfb53so4325223wme.0\n for ; Fri, 28 Jan 2022 07:30:20 -0800 (PST)","from orth.archaic.org.uk (orth.archaic.org.uk. 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Iglesias \nReviewed-by: Peter Maydell \nReviewed-by: Luc Michel \nMessage-id: 20220121161141.14389-2-francisco.iglesias@xilinx.com\nSigned-off-by: Peter Maydell \n---\n include/hw/misc/xlnx-versal-pmc-iou-slcr.h | 78 ++\n hw/misc/xlnx-versal-pmc-iou-slcr.c | 1446 ++++++++++++++++++++\n hw/misc/meson.build | 5 +-\n 3 files changed, 1528 insertions(+), 1 deletion(-)\n create mode 100644 include/hw/misc/xlnx-versal-pmc-iou-slcr.h\n create mode 100644 hw/misc/xlnx-versal-pmc-iou-slcr.c","diff":"diff --git a/include/hw/misc/xlnx-versal-pmc-iou-slcr.h b/include/hw/misc/xlnx-versal-pmc-iou-slcr.h\nnew file mode 100644\nindex 00000000000..ab4e4b4f185\n--- /dev/null\n+++ b/include/hw/misc/xlnx-versal-pmc-iou-slcr.h\n@@ -0,0 +1,78 @@\n+/*\n+ * Header file for the Xilinx Versal's PMC IOU SLCR\n+ *\n+ * Copyright (C) 2021 Xilinx Inc\n+ * Written by Edgar E. Iglesias \n+ *\n+ * Permission is hereby granted, free of charge, to any person obtaining a copy\n+ * of this software and associated documentation files (the \"Software\"), to deal\n+ * in the Software without restriction, including without limitation the rights\n+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell\n+ * copies of the Software, and to permit persons to whom the Software is\n+ * furnished to do so, subject to the following conditions:\n+ *\n+ * The above copyright notice and this permission notice shall be included in\n+ * all copies or substantial portions of the Software.\n+ *\n+ * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\n+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN\n+ * THE SOFTWARE.\n+ */\n+\n+/*\n+ * This is a model of Xilinx Versal's PMC I/O Peripheral Control and Status\n+ * module documented in Versal's Technical Reference manual [1] and the Versal\n+ * ACAP Register reference [2].\n+ *\n+ * References:\n+ *\n+ * [1] Versal ACAP Technical Reference Manual,\n+ * https://www.xilinx.com/support/documentation/architecture-manuals/am011-versal-acap-trm.pdf\n+ *\n+ * [2] Versal ACAP Register Reference,\n+ * https://www.xilinx.com/html_docs/registers/am012/am012-versal-register-reference.html#mod___pmc_iop_slcr.html\n+ *\n+ * QEMU interface:\n+ * + sysbus MMIO region 0: MemoryRegion for the device's registers\n+ * + sysbus IRQ 0: PMC (AXI and APB) parity error interrupt detected by the PMC\n+ * I/O peripherals.\n+ * + sysbus IRQ 1: Device interrupt.\n+ * + Named GPIO output \"sd-emmc-sel[0]\": Enables 0: SD mode or 1: eMMC mode on\n+ * SD/eMMC controller 0.\n+ * + Named GPIO output \"sd-emmc-sel[1]\": Enables 0: SD mode or 1: eMMC mode on\n+ * SD/eMMC controller 1.\n+ * + Named GPIO output \"qspi-ospi-mux-sel\": Selects 0: QSPI linear region or 1:\n+ * OSPI linear region.\n+ * + Named GPIO output \"ospi-mux-sel\": Selects 0: OSPI Indirect access mode or\n+ * 1: OSPI direct access mode.\n+ */\n+\n+#ifndef XILINX_VERSAL_PMC_IOU_SLCR_H\n+#define XILINX_VERSAL_PMC_IOU_SLCR_H\n+\n+#include \"hw/register.h\"\n+\n+#define TYPE_XILINX_VERSAL_PMC_IOU_SLCR \"xlnx.versal-pmc-iou-slcr\"\n+\n+OBJECT_DECLARE_SIMPLE_TYPE(XlnxVersalPmcIouSlcr, XILINX_VERSAL_PMC_IOU_SLCR)\n+\n+#define XILINX_VERSAL_PMC_IOU_SLCR_R_MAX (0x828 / 4 + 1)\n+\n+struct XlnxVersalPmcIouSlcr {\n+ SysBusDevice parent_obj;\n+ MemoryRegion iomem;\n+ qemu_irq irq_parity_imr;\n+ qemu_irq irq_imr;\n+ qemu_irq sd_emmc_sel[2];\n+ qemu_irq qspi_ospi_mux_sel;\n+ qemu_irq ospi_mux_sel;\n+\n+ uint32_t regs[XILINX_VERSAL_PMC_IOU_SLCR_R_MAX];\n+ RegisterInfo regs_info[XILINX_VERSAL_PMC_IOU_SLCR_R_MAX];\n+};\n+\n+#endif /* XILINX_VERSAL_PMC_IOU_SLCR_H */\ndiff --git a/hw/misc/xlnx-versal-pmc-iou-slcr.c b/hw/misc/xlnx-versal-pmc-iou-slcr.c\nnew file mode 100644\nindex 00000000000..07b7ebc2173\n--- /dev/null\n+++ b/hw/misc/xlnx-versal-pmc-iou-slcr.c\n@@ -0,0 +1,1446 @@\n+/*\n+ * QEMU model of Versal's PMC IOU SLCR (system level control registers)\n+ *\n+ * Copyright (c) 2021 Xilinx Inc.\n+ * Written by Edgar E. Iglesias \n+ *\n+ * Permission is hereby granted, free of charge, to any person obtaining a copy\n+ * of this software and associated documentation files (the \"Software\"), to deal\n+ * in the Software without restriction, including without limitation the rights\n+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell\n+ * copies of the Software, and to permit persons to whom the Software is\n+ * furnished to do so, subject to the following conditions:\n+ *\n+ * The above copyright notice and this permission notice shall be included in\n+ * all copies or substantial portions of the Software.\n+ *\n+ * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\n+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN\n+ * THE SOFTWARE.\n+ */\n+\n+#include \"qemu/osdep.h\"\n+#include \"hw/sysbus.h\"\n+#include \"hw/register.h\"\n+#include \"hw/irq.h\"\n+#include \"qemu/bitops.h\"\n+#include \"qemu/log.h\"\n+#include \"migration/vmstate.h\"\n+#include \"hw/qdev-properties.h\"\n+#include \"hw/misc/xlnx-versal-pmc-iou-slcr.h\"\n+\n+#ifndef XILINX_VERSAL_PMC_IOU_SLCR_ERR_DEBUG\n+#define XILINX_VERSAL_PMC_IOU_SLCR_ERR_DEBUG 0\n+#endif\n+\n+REG32(MIO_PIN_0, 0x0)\n+ FIELD(MIO_PIN_0, L3_SEL, 7, 3)\n+ FIELD(MIO_PIN_0, L2_SEL, 5, 2)\n+ FIELD(MIO_PIN_0, L1_SEL, 3, 2)\n+ FIELD(MIO_PIN_0, L0_SEL, 1, 2)\n+REG32(MIO_PIN_1, 0x4)\n+ FIELD(MIO_PIN_1, L3_SEL, 7, 3)\n+ FIELD(MIO_PIN_1, L2_SEL, 5, 2)\n+ FIELD(MIO_PIN_1, L1_SEL, 3, 2)\n+ FIELD(MIO_PIN_1, L0_SEL, 1, 2)\n+REG32(MIO_PIN_2, 0x8)\n+ FIELD(MIO_PIN_2, L3_SEL, 7, 3)\n+ FIELD(MIO_PIN_2, L2_SEL, 5, 2)\n+ FIELD(MIO_PIN_2, L1_SEL, 3, 2)\n+ FIELD(MIO_PIN_2, L0_SEL, 1, 2)\n+REG32(MIO_PIN_3, 0xc)\n+ FIELD(MIO_PIN_3, L3_SEL, 7, 3)\n+ FIELD(MIO_PIN_3, L2_SEL, 5, 2)\n+ FIELD(MIO_PIN_3, L1_SEL, 3, 2)\n+ FIELD(MIO_PIN_3, L0_SEL, 1, 2)\n+REG32(MIO_PIN_4, 0x10)\n+ FIELD(MIO_PIN_4, L3_SEL, 7, 3)\n+ FIELD(MIO_PIN_4, L2_SEL, 5, 2)\n+ FIELD(MIO_PIN_4, L1_SEL, 3, 2)\n+ FIELD(MIO_PIN_4, L0_SEL, 1, 2)\n+REG32(MIO_PIN_5, 0x14)\n+ FIELD(MIO_PIN_5, L3_SEL, 7, 3)\n+ FIELD(MIO_PIN_5, L2_SEL, 5, 2)\n+ FIELD(MIO_PIN_5, L1_SEL, 3, 2)\n+ FIELD(MIO_PIN_5, L0_SEL, 1, 2)\n+REG32(MIO_PIN_6, 0x18)\n+ FIELD(MIO_PIN_6, L3_SEL, 7, 3)\n+ FIELD(MIO_PIN_6, L2_SEL, 5, 2)\n+ FIELD(MIO_PIN_6, L1_SEL, 3, 2)\n+ FIELD(MIO_PIN_6, L0_SEL, 1, 2)\n+REG32(MIO_PIN_7, 0x1c)\n+ FIELD(MIO_PIN_7, L3_SEL, 7, 3)\n+ FIELD(MIO_PIN_7, L2_SEL, 5, 2)\n+ FIELD(MIO_PIN_7, L1_SEL, 3, 2)\n+ FIELD(MIO_PIN_7, L0_SEL, 1, 2)\n+REG32(MIO_PIN_8, 0x20)\n+ FIELD(MIO_PIN_8, L3_SEL, 7, 3)\n+ FIELD(MIO_PIN_8, L2_SEL, 5, 2)\n+ FIELD(MIO_PIN_8, L1_SEL, 3, 2)\n+ FIELD(MIO_PIN_8, L0_SEL, 1, 2)\n+REG32(MIO_PIN_9, 0x24)\n+ FIELD(MIO_PIN_9, L3_SEL, 7, 3)\n+ FIELD(MIO_PIN_9, L2_SEL, 5, 2)\n+ FIELD(MIO_PIN_9, L1_SEL, 3, 2)\n+ FIELD(MIO_PIN_9, L0_SEL, 1, 2)\n+REG32(MIO_PIN_10, 0x28)\n+ FIELD(MIO_PIN_10, L3_SEL, 7, 3)\n+ FIELD(MIO_PIN_10, L2_SEL, 5, 2)\n+ FIELD(MIO_PIN_10, L1_SEL, 3, 2)\n+ FIELD(MIO_PIN_10, L0_SEL, 1, 2)\n+REG32(MIO_PIN_11, 0x2c)\n+ FIELD(MIO_PIN_11, L3_SEL, 7, 3)\n+ FIELD(MIO_PIN_11, L2_SEL, 5, 2)\n+ FIELD(MIO_PIN_11, L1_SEL, 3, 2)\n+ FIELD(MIO_PIN_11, L0_SEL, 1, 2)\n+REG32(MIO_PIN_12, 0x30)\n+ FIELD(MIO_PIN_12, L3_SEL, 7, 3)\n+ FIELD(MIO_PIN_12, L2_SEL, 5, 2)\n+ FIELD(MIO_PIN_12, L1_SEL, 3, 2)\n+ FIELD(MIO_PIN_12, L0_SEL, 1, 2)\n+REG32(MIO_PIN_13, 0x34)\n+ FIELD(MIO_PIN_13, L3_SEL, 7, 3)\n+ FIELD(MIO_PIN_13, L2_SEL, 5, 2)\n+ FIELD(MIO_PIN_13, L1_SEL, 3, 2)\n+ FIELD(MIO_PIN_13, L0_SEL, 1, 2)\n+REG32(MIO_PIN_14, 0x38)\n+ FIELD(MIO_PIN_14, L3_SEL, 7, 3)\n+ FIELD(MIO_PIN_14, L2_SEL, 5, 2)\n+ FIELD(MIO_PIN_14, L1_SEL, 3, 2)\n+ FIELD(MIO_PIN_14, L0_SEL, 1, 2)\n+REG32(MIO_PIN_15, 0x3c)\n+ FIELD(MIO_PIN_15, L3_SEL, 7, 3)\n+ FIELD(MIO_PIN_15, L2_SEL, 5, 2)\n+ FIELD(MIO_PIN_15, L1_SEL, 3, 2)\n+ FIELD(MIO_PIN_15, L0_SEL, 1, 2)\n+REG32(MIO_PIN_16, 0x40)\n+ FIELD(MIO_PIN_16, L3_SEL, 7, 3)\n+ FIELD(MIO_PIN_16, L2_SEL, 5, 2)\n+ FIELD(MIO_PIN_16, L1_SEL, 3, 2)\n+ FIELD(MIO_PIN_16, L0_SEL, 1, 2)\n+REG32(MIO_PIN_17, 0x44)\n+ FIELD(MIO_PIN_17, L3_SEL, 7, 3)\n+ FIELD(MIO_PIN_17, L2_SEL, 5, 2)\n+ FIELD(MIO_PIN_17, L1_SEL, 3, 2)\n+ FIELD(MIO_PIN_17, L0_SEL, 1, 2)\n+REG32(MIO_PIN_18, 0x48)\n+ FIELD(MIO_PIN_18, L3_SEL, 7, 3)\n+ FIELD(MIO_PIN_18, L2_SEL, 5, 2)\n+ FIELD(MIO_PIN_18, L1_SEL, 3, 2)\n+ FIELD(MIO_PIN_18, L0_SEL, 1, 2)\n+REG32(MIO_PIN_19, 0x4c)\n+ FIELD(MIO_PIN_19, L3_SEL, 7, 3)\n+ FIELD(MIO_PIN_19, L2_SEL, 5, 2)\n+ FIELD(MIO_PIN_19, L1_SEL, 3, 2)\n+ FIELD(MIO_PIN_19, L0_SEL, 1, 2)\n+REG32(MIO_PIN_20, 0x50)\n+ FIELD(MIO_PIN_20, L3_SEL, 7, 3)\n+ FIELD(MIO_PIN_20, L2_SEL, 5, 2)\n+ FIELD(MIO_PIN_20, L1_SEL, 3, 2)\n+ FIELD(MIO_PIN_20, L0_SEL, 1, 2)\n+REG32(MIO_PIN_21, 0x54)\n+ FIELD(MIO_PIN_21, L3_SEL, 7, 3)\n+ FIELD(MIO_PIN_21, L2_SEL, 5, 2)\n+ FIELD(MIO_PIN_21, L1_SEL, 3, 2)\n+ FIELD(MIO_PIN_21, L0_SEL, 1, 2)\n+REG32(MIO_PIN_22, 0x58)\n+ FIELD(MIO_PIN_22, L3_SEL, 7, 3)\n+ FIELD(MIO_PIN_22, L2_SEL, 5, 2)\n+ FIELD(MIO_PIN_22, L1_SEL, 3, 2)\n+ FIELD(MIO_PIN_22, L0_SEL, 1, 2)\n+REG32(MIO_PIN_23, 0x5c)\n+ FIELD(MIO_PIN_23, L3_SEL, 7, 3)\n+ FIELD(MIO_PIN_23, L2_SEL, 5, 2)\n+ FIELD(MIO_PIN_23, L1_SEL, 3, 2)\n+ FIELD(MIO_PIN_23, L0_SEL, 1, 2)\n+REG32(MIO_PIN_24, 0x60)\n+ FIELD(MIO_PIN_24, L3_SEL, 7, 3)\n+ FIELD(MIO_PIN_24, L2_SEL, 5, 2)\n+ FIELD(MIO_PIN_24, L1_SEL, 3, 2)\n+ FIELD(MIO_PIN_24, L0_SEL, 1, 2)\n+REG32(MIO_PIN_25, 0x64)\n+ FIELD(MIO_PIN_25, L3_SEL, 7, 3)\n+ FIELD(MIO_PIN_25, L2_SEL, 5, 2)\n+ FIELD(MIO_PIN_25, L1_SEL, 3, 2)\n+ FIELD(MIO_PIN_25, L0_SEL, 1, 2)\n+REG32(MIO_PIN_26, 0x68)\n+ FIELD(MIO_PIN_26, L3_SEL, 7, 3)\n+ FIELD(MIO_PIN_26, L2_SEL, 5, 2)\n+ FIELD(MIO_PIN_26, L1_SEL, 3, 2)\n+ FIELD(MIO_PIN_26, L0_SEL, 1, 2)\n+REG32(MIO_PIN_27, 0x6c)\n+ FIELD(MIO_PIN_27, L3_SEL, 7, 3)\n+ FIELD(MIO_PIN_27, L2_SEL, 5, 2)\n+ FIELD(MIO_PIN_27, L1_SEL, 3, 2)\n+ FIELD(MIO_PIN_27, L0_SEL, 1, 2)\n+REG32(MIO_PIN_28, 0x70)\n+ FIELD(MIO_PIN_28, L3_SEL, 7, 3)\n+ FIELD(MIO_PIN_28, L2_SEL, 5, 2)\n+ FIELD(MIO_PIN_28, L1_SEL, 3, 2)\n+ FIELD(MIO_PIN_28, L0_SEL, 1, 2)\n+REG32(MIO_PIN_29, 0x74)\n+ FIELD(MIO_PIN_29, L3_SEL, 7, 3)\n+ FIELD(MIO_PIN_29, L2_SEL, 5, 2)\n+ FIELD(MIO_PIN_29, L1_SEL, 3, 2)\n+ FIELD(MIO_PIN_29, L0_SEL, 1, 2)\n+REG32(MIO_PIN_30, 0x78)\n+ FIELD(MIO_PIN_30, L3_SEL, 7, 3)\n+ FIELD(MIO_PIN_30, L2_SEL, 5, 2)\n+ FIELD(MIO_PIN_30, L1_SEL, 3, 2)\n+ FIELD(MIO_PIN_30, L0_SEL, 1, 2)\n+REG32(MIO_PIN_31, 0x7c)\n+ FIELD(MIO_PIN_31, L3_SEL, 7, 3)\n+ FIELD(MIO_PIN_31, L2_SEL, 5, 2)\n+ FIELD(MIO_PIN_31, L1_SEL, 3, 2)\n+ FIELD(MIO_PIN_31, L0_SEL, 1, 2)\n+REG32(MIO_PIN_32, 0x80)\n+ FIELD(MIO_PIN_32, L3_SEL, 7, 3)\n+ FIELD(MIO_PIN_32, L2_SEL, 5, 2)\n+ FIELD(MIO_PIN_32, L1_SEL, 3, 2)\n+ FIELD(MIO_PIN_32, L0_SEL, 1, 2)\n+REG32(MIO_PIN_33, 0x84)\n+ FIELD(MIO_PIN_33, L3_SEL, 7, 3)\n+ FIELD(MIO_PIN_33, L2_SEL, 5, 2)\n+ FIELD(MIO_PIN_33, L1_SEL, 3, 2)\n+ FIELD(MIO_PIN_33, L0_SEL, 1, 2)\n+REG32(MIO_PIN_34, 0x88)\n+ FIELD(MIO_PIN_34, L3_SEL, 7, 3)\n+ FIELD(MIO_PIN_34, L2_SEL, 5, 2)\n+ FIELD(MIO_PIN_34, L1_SEL, 3, 2)\n+ FIELD(MIO_PIN_34, L0_SEL, 1, 2)\n+REG32(MIO_PIN_35, 0x8c)\n+ FIELD(MIO_PIN_35, L3_SEL, 7, 3)\n+ FIELD(MIO_PIN_35, L2_SEL, 5, 2)\n+ FIELD(MIO_PIN_35, L1_SEL, 3, 2)\n+ FIELD(MIO_PIN_35, L0_SEL, 1, 2)\n+REG32(MIO_PIN_36, 0x90)\n+ FIELD(MIO_PIN_36, L3_SEL, 7, 3)\n+ FIELD(MIO_PIN_36, L2_SEL, 5, 2)\n+ FIELD(MIO_PIN_36, L1_SEL, 3, 2)\n+ FIELD(MIO_PIN_36, L0_SEL, 1, 2)\n+REG32(MIO_PIN_37, 0x94)\n+ FIELD(MIO_PIN_37, L3_SEL, 7, 3)\n+ FIELD(MIO_PIN_37, L2_SEL, 5, 2)\n+ FIELD(MIO_PIN_37, L1_SEL, 3, 2)\n+ FIELD(MIO_PIN_37, L0_SEL, 1, 2)\n+REG32(MIO_PIN_38, 0x98)\n+ FIELD(MIO_PIN_38, L3_SEL, 7, 3)\n+ FIELD(MIO_PIN_38, L2_SEL, 5, 2)\n+ FIELD(MIO_PIN_38, L1_SEL, 3, 2)\n+ FIELD(MIO_PIN_38, L0_SEL, 1, 2)\n+REG32(MIO_PIN_39, 0x9c)\n+ FIELD(MIO_PIN_39, L3_SEL, 7, 3)\n+ FIELD(MIO_PIN_39, L2_SEL, 5, 2)\n+ FIELD(MIO_PIN_39, L1_SEL, 3, 2)\n+ FIELD(MIO_PIN_39, L0_SEL, 1, 2)\n+REG32(MIO_PIN_40, 0xa0)\n+ FIELD(MIO_PIN_40, L3_SEL, 7, 3)\n+ FIELD(MIO_PIN_40, L2_SEL, 5, 2)\n+ FIELD(MIO_PIN_40, L1_SEL, 3, 2)\n+ FIELD(MIO_PIN_40, L0_SEL, 1, 2)\n+REG32(MIO_PIN_41, 0xa4)\n+ FIELD(MIO_PIN_41, L3_SEL, 7, 3)\n+ FIELD(MIO_PIN_41, L2_SEL, 5, 2)\n+ FIELD(MIO_PIN_41, L1_SEL, 3, 2)\n+ FIELD(MIO_PIN_41, L0_SEL, 1, 2)\n+REG32(MIO_PIN_42, 0xa8)\n+ FIELD(MIO_PIN_42, L3_SEL, 7, 3)\n+ FIELD(MIO_PIN_42, L2_SEL, 5, 2)\n+ FIELD(MIO_PIN_42, L1_SEL, 3, 2)\n+ FIELD(MIO_PIN_42, L0_SEL, 1, 2)\n+REG32(MIO_PIN_43, 0xac)\n+ FIELD(MIO_PIN_43, L3_SEL, 7, 3)\n+ FIELD(MIO_PIN_43, L2_SEL, 5, 2)\n+ FIELD(MIO_PIN_43, L1_SEL, 3, 2)\n+ FIELD(MIO_PIN_43, L0_SEL, 1, 2)\n+REG32(MIO_PIN_44, 0xb0)\n+ FIELD(MIO_PIN_44, L3_SEL, 7, 3)\n+ FIELD(MIO_PIN_44, L2_SEL, 5, 2)\n+ FIELD(MIO_PIN_44, L1_SEL, 3, 2)\n+ FIELD(MIO_PIN_44, L0_SEL, 1, 2)\n+REG32(MIO_PIN_45, 0xb4)\n+ FIELD(MIO_PIN_45, L3_SEL, 7, 3)\n+ FIELD(MIO_PIN_45, L2_SEL, 5, 2)\n+ FIELD(MIO_PIN_45, L1_SEL, 3, 2)\n+ FIELD(MIO_PIN_45, L0_SEL, 1, 2)\n+REG32(MIO_PIN_46, 0xb8)\n+ FIELD(MIO_PIN_46, L3_SEL, 7, 3)\n+ FIELD(MIO_PIN_46, L2_SEL, 5, 2)\n+ FIELD(MIO_PIN_46, L1_SEL, 3, 2)\n+ FIELD(MIO_PIN_46, L0_SEL, 1, 2)\n+REG32(MIO_PIN_47, 0xbc)\n+ FIELD(MIO_PIN_47, L3_SEL, 7, 3)\n+ FIELD(MIO_PIN_47, L2_SEL, 5, 2)\n+ FIELD(MIO_PIN_47, L1_SEL, 3, 2)\n+ FIELD(MIO_PIN_47, L0_SEL, 1, 2)\n+REG32(MIO_PIN_48, 0xc0)\n+ FIELD(MIO_PIN_48, L3_SEL, 7, 3)\n+ FIELD(MIO_PIN_48, L2_SEL, 5, 2)\n+ FIELD(MIO_PIN_48, L1_SEL, 3, 2)\n+ FIELD(MIO_PIN_48, L0_SEL, 1, 2)\n+REG32(MIO_PIN_49, 0xc4)\n+ FIELD(MIO_PIN_49, L3_SEL, 7, 3)\n+ FIELD(MIO_PIN_49, L2_SEL, 5, 2)\n+ FIELD(MIO_PIN_49, L1_SEL, 3, 2)\n+ FIELD(MIO_PIN_49, L0_SEL, 1, 2)\n+REG32(MIO_PIN_50, 0xc8)\n+ FIELD(MIO_PIN_50, L3_SEL, 7, 3)\n+ FIELD(MIO_PIN_50, L2_SEL, 5, 2)\n+ FIELD(MIO_PIN_50, L1_SEL, 3, 2)\n+ FIELD(MIO_PIN_50, L0_SEL, 1, 2)\n+REG32(MIO_PIN_51, 0xcc)\n+ FIELD(MIO_PIN_51, L3_SEL, 7, 3)\n+ FIELD(MIO_PIN_51, L2_SEL, 5, 2)\n+ FIELD(MIO_PIN_51, L1_SEL, 3, 2)\n+ FIELD(MIO_PIN_51, L0_SEL, 1, 2)\n+REG32(BNK0_EN_RX, 0x100)\n+ FIELD(BNK0_EN_RX, BNK0_EN_RX, 0, 26)\n+REG32(BNK0_SEL_RX0, 0x104)\n+REG32(BNK0_SEL_RX1, 0x108)\n+ FIELD(BNK0_SEL_RX1, BNK0_SEL_RX, 0, 20)\n+REG32(BNK0_EN_RX_SCHMITT_HYST, 0x10c)\n+ FIELD(BNK0_EN_RX_SCHMITT_HYST, BNK0_EN_RX_SCHMITT_HYST, 0, 26)\n+REG32(BNK0_EN_WK_PD, 0x110)\n+ FIELD(BNK0_EN_WK_PD, BNK0_EN_WK_PD, 0, 26)\n+REG32(BNK0_EN_WK_PU, 0x114)\n+ FIELD(BNK0_EN_WK_PU, BNK0_EN_WK_PU, 0, 26)\n+REG32(BNK0_SEL_DRV0, 0x118)\n+REG32(BNK0_SEL_DRV1, 0x11c)\n+ FIELD(BNK0_SEL_DRV1, BNK0_SEL_DRV, 0, 20)\n+REG32(BNK0_SEL_SLEW, 0x120)\n+ FIELD(BNK0_SEL_SLEW, BNK0_SEL_SLEW, 0, 26)\n+REG32(BNK0_EN_DFT_OPT_INV, 0x124)\n+ FIELD(BNK0_EN_DFT_OPT_INV, BNK0_EN_DFT_OPT_INV, 0, 26)\n+REG32(BNK0_EN_PAD2PAD_LOOPBACK, 0x128)\n+ FIELD(BNK0_EN_PAD2PAD_LOOPBACK, BNK0_EN_PAD2PAD_LOOPBACK, 0, 13)\n+REG32(BNK0_RX_SPARE0, 0x12c)\n+REG32(BNK0_RX_SPARE1, 0x130)\n+ FIELD(BNK0_RX_SPARE1, BNK0_RX_SPARE, 0, 20)\n+REG32(BNK0_TX_SPARE0, 0x134)\n+REG32(BNK0_TX_SPARE1, 0x138)\n+ FIELD(BNK0_TX_SPARE1, BNK0_TX_SPARE, 0, 20)\n+REG32(BNK0_SEL_EN1P8, 0x13c)\n+ FIELD(BNK0_SEL_EN1P8, BNK0_SEL_EN1P8, 0, 1)\n+REG32(BNK0_EN_B_POR_DETECT, 0x140)\n+ FIELD(BNK0_EN_B_POR_DETECT, BNK0_EN_B_POR_DETECT, 0, 1)\n+REG32(BNK0_LPF_BYP_POR_DETECT, 0x144)\n+ FIELD(BNK0_LPF_BYP_POR_DETECT, BNK0_LPF_BYP_POR_DETECT, 0, 1)\n+REG32(BNK0_EN_LATCH, 0x148)\n+ FIELD(BNK0_EN_LATCH, BNK0_EN_LATCH, 0, 1)\n+REG32(BNK0_VBG_LPF_BYP_B, 0x14c)\n+ FIELD(BNK0_VBG_LPF_BYP_B, BNK0_VBG_LPF_BYP_B, 0, 1)\n+REG32(BNK0_EN_AMP_B, 0x150)\n+ FIELD(BNK0_EN_AMP_B, BNK0_EN_AMP_B, 0, 2)\n+REG32(BNK0_SPARE_BIAS, 0x154)\n+ FIELD(BNK0_SPARE_BIAS, BNK0_SPARE_BIAS, 0, 4)\n+REG32(BNK0_DRIVER_BIAS, 0x158)\n+ FIELD(BNK0_DRIVER_BIAS, BNK0_DRIVER_BIAS, 0, 15)\n+REG32(BNK0_VMODE, 0x15c)\n+ FIELD(BNK0_VMODE, BNK0_VMODE, 0, 1)\n+REG32(BNK0_SEL_AUX_IO_RX, 0x160)\n+ FIELD(BNK0_SEL_AUX_IO_RX, BNK0_SEL_AUX_IO_RX, 0, 26)\n+REG32(BNK0_EN_TX_HS_MODE, 0x164)\n+ FIELD(BNK0_EN_TX_HS_MODE, BNK0_EN_TX_HS_MODE, 0, 26)\n+REG32(MIO_MST_TRI0, 0x200)\n+ FIELD(MIO_MST_TRI0, PIN_25_TRI, 25, 1)\n+ FIELD(MIO_MST_TRI0, PIN_24_TRI, 24, 1)\n+ FIELD(MIO_MST_TRI0, PIN_23_TRI, 23, 1)\n+ FIELD(MIO_MST_TRI0, PIN_22_TRI, 22, 1)\n+ FIELD(MIO_MST_TRI0, PIN_21_TRI, 21, 1)\n+ FIELD(MIO_MST_TRI0, PIN_20_TRI, 20, 1)\n+ FIELD(MIO_MST_TRI0, PIN_19_TRI, 19, 1)\n+ FIELD(MIO_MST_TRI0, PIN_18_TRI, 18, 1)\n+ FIELD(MIO_MST_TRI0, PIN_17_TRI, 17, 1)\n+ FIELD(MIO_MST_TRI0, PIN_16_TRI, 16, 1)\n+ FIELD(MIO_MST_TRI0, PIN_15_TRI, 15, 1)\n+ FIELD(MIO_MST_TRI0, PIN_14_TRI, 14, 1)\n+ FIELD(MIO_MST_TRI0, PIN_13_TRI, 13, 1)\n+ FIELD(MIO_MST_TRI0, PIN_12_TRI, 12, 1)\n+ FIELD(MIO_MST_TRI0, PIN_11_TRI, 11, 1)\n+ FIELD(MIO_MST_TRI0, PIN_10_TRI, 10, 1)\n+ FIELD(MIO_MST_TRI0, PIN_09_TRI, 9, 1)\n+ FIELD(MIO_MST_TRI0, PIN_08_TRI, 8, 1)\n+ FIELD(MIO_MST_TRI0, PIN_07_TRI, 7, 1)\n+ FIELD(MIO_MST_TRI0, PIN_06_TRI, 6, 1)\n+ FIELD(MIO_MST_TRI0, PIN_05_TRI, 5, 1)\n+ FIELD(MIO_MST_TRI0, PIN_04_TRI, 4, 1)\n+ FIELD(MIO_MST_TRI0, PIN_03_TRI, 3, 1)\n+ FIELD(MIO_MST_TRI0, PIN_02_TRI, 2, 1)\n+ FIELD(MIO_MST_TRI0, PIN_01_TRI, 1, 1)\n+ FIELD(MIO_MST_TRI0, PIN_00_TRI, 0, 1)\n+REG32(MIO_MST_TRI1, 0x204)\n+ FIELD(MIO_MST_TRI1, PIN_51_TRI, 25, 1)\n+ FIELD(MIO_MST_TRI1, PIN_50_TRI, 24, 1)\n+ FIELD(MIO_MST_TRI1, PIN_49_TRI, 23, 1)\n+ FIELD(MIO_MST_TRI1, PIN_48_TRI, 22, 1)\n+ FIELD(MIO_MST_TRI1, PIN_47_TRI, 21, 1)\n+ FIELD(MIO_MST_TRI1, PIN_46_TRI, 20, 1)\n+ FIELD(MIO_MST_TRI1, PIN_45_TRI, 19, 1)\n+ FIELD(MIO_MST_TRI1, PIN_44_TRI, 18, 1)\n+ FIELD(MIO_MST_TRI1, PIN_43_TRI, 17, 1)\n+ FIELD(MIO_MST_TRI1, PIN_42_TRI, 16, 1)\n+ FIELD(MIO_MST_TRI1, PIN_41_TRI, 15, 1)\n+ FIELD(MIO_MST_TRI1, PIN_40_TRI, 14, 1)\n+ FIELD(MIO_MST_TRI1, PIN_39_TRI, 13, 1)\n+ FIELD(MIO_MST_TRI1, PIN_38_TRI, 12, 1)\n+ FIELD(MIO_MST_TRI1, PIN_37_TRI, 11, 1)\n+ FIELD(MIO_MST_TRI1, PIN_36_TRI, 10, 1)\n+ FIELD(MIO_MST_TRI1, PIN_35_TRI, 9, 1)\n+ FIELD(MIO_MST_TRI1, PIN_34_TRI, 8, 1)\n+ FIELD(MIO_MST_TRI1, PIN_33_TRI, 7, 1)\n+ FIELD(MIO_MST_TRI1, PIN_32_TRI, 6, 1)\n+ FIELD(MIO_MST_TRI1, PIN_31_TRI, 5, 1)\n+ FIELD(MIO_MST_TRI1, PIN_30_TRI, 4, 1)\n+ FIELD(MIO_MST_TRI1, PIN_29_TRI, 3, 1)\n+ FIELD(MIO_MST_TRI1, PIN_28_TRI, 2, 1)\n+ FIELD(MIO_MST_TRI1, PIN_27_TRI, 1, 1)\n+ FIELD(MIO_MST_TRI1, PIN_26_TRI, 0, 1)\n+REG32(BNK1_EN_RX, 0x300)\n+ FIELD(BNK1_EN_RX, BNK1_EN_RX, 0, 26)\n+REG32(BNK1_SEL_RX0, 0x304)\n+REG32(BNK1_SEL_RX1, 0x308)\n+ FIELD(BNK1_SEL_RX1, BNK1_SEL_RX, 0, 20)\n+REG32(BNK1_EN_RX_SCHMITT_HYST, 0x30c)\n+ FIELD(BNK1_EN_RX_SCHMITT_HYST, BNK1_EN_RX_SCHMITT_HYST, 0, 26)\n+REG32(BNK1_EN_WK_PD, 0x310)\n+ FIELD(BNK1_EN_WK_PD, BNK1_EN_WK_PD, 0, 26)\n+REG32(BNK1_EN_WK_PU, 0x314)\n+ FIELD(BNK1_EN_WK_PU, BNK1_EN_WK_PU, 0, 26)\n+REG32(BNK1_SEL_DRV0, 0x318)\n+REG32(BNK1_SEL_DRV1, 0x31c)\n+ FIELD(BNK1_SEL_DRV1, BNK1_SEL_DRV, 0, 20)\n+REG32(BNK1_SEL_SLEW, 0x320)\n+ FIELD(BNK1_SEL_SLEW, BNK1_SEL_SLEW, 0, 26)\n+REG32(BNK1_EN_DFT_OPT_INV, 0x324)\n+ FIELD(BNK1_EN_DFT_OPT_INV, BNK1_EN_DFT_OPT_INV, 0, 26)\n+REG32(BNK1_EN_PAD2PAD_LOOPBACK, 0x328)\n+ FIELD(BNK1_EN_PAD2PAD_LOOPBACK, BNK1_EN_PAD2PAD_LOOPBACK, 0, 13)\n+REG32(BNK1_RX_SPARE0, 0x32c)\n+REG32(BNK1_RX_SPARE1, 0x330)\n+ FIELD(BNK1_RX_SPARE1, BNK1_RX_SPARE, 0, 20)\n+REG32(BNK1_TX_SPARE0, 0x334)\n+REG32(BNK1_TX_SPARE1, 0x338)\n+ FIELD(BNK1_TX_SPARE1, BNK1_TX_SPARE, 0, 20)\n+REG32(BNK1_SEL_EN1P8, 0x33c)\n+ FIELD(BNK1_SEL_EN1P8, BNK1_SEL_EN1P8, 0, 1)\n+REG32(BNK1_EN_B_POR_DETECT, 0x340)\n+ FIELD(BNK1_EN_B_POR_DETECT, BNK1_EN_B_POR_DETECT, 0, 1)\n+REG32(BNK1_LPF_BYP_POR_DETECT, 0x344)\n+ FIELD(BNK1_LPF_BYP_POR_DETECT, BNK1_LPF_BYP_POR_DETECT, 0, 1)\n+REG32(BNK1_EN_LATCH, 0x348)\n+ FIELD(BNK1_EN_LATCH, BNK1_EN_LATCH, 0, 1)\n+REG32(BNK1_VBG_LPF_BYP_B, 0x34c)\n+ FIELD(BNK1_VBG_LPF_BYP_B, BNK1_VBG_LPF_BYP_B, 0, 1)\n+REG32(BNK1_EN_AMP_B, 0x350)\n+ FIELD(BNK1_EN_AMP_B, BNK1_EN_AMP_B, 0, 2)\n+REG32(BNK1_SPARE_BIAS, 0x354)\n+ FIELD(BNK1_SPARE_BIAS, BNK1_SPARE_BIAS, 0, 4)\n+REG32(BNK1_DRIVER_BIAS, 0x358)\n+ FIELD(BNK1_DRIVER_BIAS, BNK1_DRIVER_BIAS, 0, 15)\n+REG32(BNK1_VMODE, 0x35c)\n+ FIELD(BNK1_VMODE, BNK1_VMODE, 0, 1)\n+REG32(BNK1_SEL_AUX_IO_RX, 0x360)\n+ FIELD(BNK1_SEL_AUX_IO_RX, BNK1_SEL_AUX_IO_RX, 0, 26)\n+REG32(BNK1_EN_TX_HS_MODE, 0x364)\n+ FIELD(BNK1_EN_TX_HS_MODE, BNK1_EN_TX_HS_MODE, 0, 26)\n+REG32(SD0_CLK_CTRL, 0x400)\n+ FIELD(SD0_CLK_CTRL, SDIO0_FBCLK_SEL, 2, 1)\n+ FIELD(SD0_CLK_CTRL, SDIO0_RX_SRC_SEL, 0, 2)\n+REG32(SD0_CTRL_REG, 0x404)\n+ FIELD(SD0_CTRL_REG, SD0_EMMC_SEL, 0, 1)\n+REG32(SD0_CONFIG_REG1, 0x410)\n+ FIELD(SD0_CONFIG_REG1, SD0_BASECLK, 7, 8)\n+ FIELD(SD0_CONFIG_REG1, SD0_TUNIGCOUNT, 1, 6)\n+ FIELD(SD0_CONFIG_REG1, SD0_ASYNCWKPENA, 0, 1)\n+REG32(SD0_CONFIG_REG2, 0x414)\n+ FIELD(SD0_CONFIG_REG2, SD0_SLOTTYPE, 12, 2)\n+ FIELD(SD0_CONFIG_REG2, SD0_ASYCINTR, 11, 1)\n+ FIELD(SD0_CONFIG_REG2, SD0_64BIT, 10, 1)\n+ FIELD(SD0_CONFIG_REG2, SD0_1P8V, 9, 1)\n+ FIELD(SD0_CONFIG_REG2, SD0_3P0V, 8, 1)\n+ FIELD(SD0_CONFIG_REG2, SD0_3P3V, 7, 1)\n+ FIELD(SD0_CONFIG_REG2, SD0_SUSPRES, 6, 1)\n+ FIELD(SD0_CONFIG_REG2, SD0_SDMA, 5, 1)\n+ FIELD(SD0_CONFIG_REG2, SD0_HIGHSPEED, 4, 1)\n+ FIELD(SD0_CONFIG_REG2, SD0_ADMA2, 3, 1)\n+ FIELD(SD0_CONFIG_REG2, SD0_8BIT, 2, 1)\n+ FIELD(SD0_CONFIG_REG2, SD0_MAXBLK, 0, 2)\n+REG32(SD0_CONFIG_REG3, 0x418)\n+ FIELD(SD0_CONFIG_REG3, SD0_TUNINGSDR50, 10, 1)\n+ FIELD(SD0_CONFIG_REG3, SD0_RETUNETMR, 6, 4)\n+ FIELD(SD0_CONFIG_REG3, SD0_DDRIVER, 5, 1)\n+ FIELD(SD0_CONFIG_REG3, SD0_CDRIVER, 4, 1)\n+ FIELD(SD0_CONFIG_REG3, SD0_ADRIVER, 3, 1)\n+ FIELD(SD0_CONFIG_REG3, SD0_DDR50, 2, 1)\n+ FIELD(SD0_CONFIG_REG3, SD0_SDR104, 1, 1)\n+ FIELD(SD0_CONFIG_REG3, SD0_SDR50, 0, 1)\n+REG32(SD0_INITPRESET, 0x41c)\n+ FIELD(SD0_INITPRESET, SD0_INITPRESET, 0, 13)\n+REG32(SD0_DSPPRESET, 0x420)\n+ FIELD(SD0_DSPPRESET, SD0_DSPPRESET, 0, 13)\n+REG32(SD0_HSPDPRESET, 0x424)\n+ FIELD(SD0_HSPDPRESET, SD0_HSPDPRESET, 0, 13)\n+REG32(SD0_SDR12PRESET, 0x428)\n+ FIELD(SD0_SDR12PRESET, SD0_SDR12PRESET, 0, 13)\n+REG32(SD0_SDR25PRESET, 0x42c)\n+ FIELD(SD0_SDR25PRESET, SD0_SDR25PRESET, 0, 13)\n+REG32(SD0_SDR50PRSET, 0x430)\n+ FIELD(SD0_SDR50PRSET, SD0_SDR50PRESET, 0, 13)\n+REG32(SD0_SDR104PRST, 0x434)\n+ FIELD(SD0_SDR104PRST, SD0_SDR104PRESET, 0, 13)\n+REG32(SD0_DDR50PRESET, 0x438)\n+ FIELD(SD0_DDR50PRESET, SD0_DDR50PRESET, 0, 13)\n+REG32(SD0_MAXCUR1P8, 0x43c)\n+ FIELD(SD0_MAXCUR1P8, SD0_MAXCUR1P8, 0, 8)\n+REG32(SD0_MAXCUR3P0, 0x440)\n+ FIELD(SD0_MAXCUR3P0, SD0_MAXCUR3P0, 0, 8)\n+REG32(SD0_MAXCUR3P3, 0x444)\n+ FIELD(SD0_MAXCUR3P3, SD0_MAXCUR3P3, 0, 8)\n+REG32(SD0_DLL_CTRL, 0x448)\n+ FIELD(SD0_DLL_CTRL, SD0_CLKSTABLE_CFG, 9, 1)\n+ FIELD(SD0_DLL_CTRL, SD0_DLL_CFG, 5, 4)\n+ FIELD(SD0_DLL_CTRL, SD0_DLL_PSDONE, 4, 1)\n+ FIELD(SD0_DLL_CTRL, SD0_DLL_OVF, 3, 1)\n+ FIELD(SD0_DLL_CTRL, SD0_DLL_RST, 2, 1)\n+ FIELD(SD0_DLL_CTRL, SD0_DLL_TESTMODE, 1, 1)\n+ FIELD(SD0_DLL_CTRL, SD0_DLL_LOCK, 0, 1)\n+REG32(SD0_CDN_CTRL, 0x44c)\n+ FIELD(SD0_CDN_CTRL, SD0_CDN_CTRL, 0, 1)\n+REG32(SD0_DLL_TEST, 0x450)\n+ FIELD(SD0_DLL_TEST, DLL_DIV, 16, 8)\n+ FIELD(SD0_DLL_TEST, DLL_TX_SEL, 9, 7)\n+ FIELD(SD0_DLL_TEST, DLL_RX_SEL, 0, 9)\n+REG32(SD0_RX_TUNING_SEL, 0x454)\n+ FIELD(SD0_RX_TUNING_SEL, SD0_RX_SEL, 0, 9)\n+REG32(SD0_DLL_DIV_MAP0, 0x458)\n+ FIELD(SD0_DLL_DIV_MAP0, DIV_3, 24, 8)\n+ FIELD(SD0_DLL_DIV_MAP0, DIV_2, 16, 8)\n+ FIELD(SD0_DLL_DIV_MAP0, DIV_1, 8, 8)\n+ FIELD(SD0_DLL_DIV_MAP0, DIV_0, 0, 8)\n+REG32(SD0_DLL_DIV_MAP1, 0x45c)\n+ FIELD(SD0_DLL_DIV_MAP1, DIV_7, 24, 8)\n+ FIELD(SD0_DLL_DIV_MAP1, DIV_6, 16, 8)\n+ FIELD(SD0_DLL_DIV_MAP1, DIV_5, 8, 8)\n+ FIELD(SD0_DLL_DIV_MAP1, DIV_4, 0, 8)\n+REG32(SD0_IOU_COHERENT_CTRL, 0x460)\n+ FIELD(SD0_IOU_COHERENT_CTRL, SD0_AXI_COH, 0, 4)\n+REG32(SD0_IOU_INTERCONNECT_ROUTE, 0x464)\n+ FIELD(SD0_IOU_INTERCONNECT_ROUTE, SD0, 0, 1)\n+REG32(SD0_IOU_RAM, 0x468)\n+ FIELD(SD0_IOU_RAM, EMASA0, 6, 1)\n+ FIELD(SD0_IOU_RAM, EMAB0, 3, 3)\n+ FIELD(SD0_IOU_RAM, EMAA0, 0, 3)\n+REG32(SD0_IOU_INTERCONNECT_QOS, 0x46c)\n+ FIELD(SD0_IOU_INTERCONNECT_QOS, SD0_QOS, 0, 4)\n+REG32(SD1_CLK_CTRL, 0x480)\n+ FIELD(SD1_CLK_CTRL, SDIO1_FBCLK_SEL, 1, 1)\n+ FIELD(SD1_CLK_CTRL, SDIO1_RX_SRC_SEL, 0, 1)\n+REG32(SD1_CTRL_REG, 0x484)\n+ FIELD(SD1_CTRL_REG, SD1_EMMC_SEL, 0, 1)\n+REG32(SD1_CONFIG_REG1, 0x490)\n+ FIELD(SD1_CONFIG_REG1, SD1_BASECLK, 7, 8)\n+ FIELD(SD1_CONFIG_REG1, SD1_TUNIGCOUNT, 1, 6)\n+ FIELD(SD1_CONFIG_REG1, SD1_ASYNCWKPENA, 0, 1)\n+REG32(SD1_CONFIG_REG2, 0x494)\n+ FIELD(SD1_CONFIG_REG2, SD1_SLOTTYPE, 12, 2)\n+ FIELD(SD1_CONFIG_REG2, SD1_ASYCINTR, 11, 1)\n+ FIELD(SD1_CONFIG_REG2, SD1_64BIT, 10, 1)\n+ FIELD(SD1_CONFIG_REG2, SD1_1P8V, 9, 1)\n+ FIELD(SD1_CONFIG_REG2, SD1_3P0V, 8, 1)\n+ FIELD(SD1_CONFIG_REG2, SD1_3P3V, 7, 1)\n+ FIELD(SD1_CONFIG_REG2, SD1_SUSPRES, 6, 1)\n+ FIELD(SD1_CONFIG_REG2, SD1_SDMA, 5, 1)\n+ FIELD(SD1_CONFIG_REG2, SD1_HIGHSPEED, 4, 1)\n+ FIELD(SD1_CONFIG_REG2, SD1_ADMA2, 3, 1)\n+ FIELD(SD1_CONFIG_REG2, SD1_8BIT, 2, 1)\n+ FIELD(SD1_CONFIG_REG2, SD1_MAXBLK, 0, 2)\n+REG32(SD1_CONFIG_REG3, 0x498)\n+ FIELD(SD1_CONFIG_REG3, SD1_TUNINGSDR50, 10, 1)\n+ FIELD(SD1_CONFIG_REG3, SD1_RETUNETMR, 6, 4)\n+ FIELD(SD1_CONFIG_REG3, SD1_DDRIVER, 5, 1)\n+ FIELD(SD1_CONFIG_REG3, SD1_CDRIVER, 4, 1)\n+ FIELD(SD1_CONFIG_REG3, SD1_ADRIVER, 3, 1)\n+ FIELD(SD1_CONFIG_REG3, SD1_DDR50, 2, 1)\n+ FIELD(SD1_CONFIG_REG3, SD1_SDR104, 1, 1)\n+ FIELD(SD1_CONFIG_REG3, SD1_SDR50, 0, 1)\n+REG32(SD1_INITPRESET, 0x49c)\n+ FIELD(SD1_INITPRESET, SD1_INITPRESET, 0, 13)\n+REG32(SD1_DSPPRESET, 0x4a0)\n+ FIELD(SD1_DSPPRESET, SD1_DSPPRESET, 0, 13)\n+REG32(SD1_HSPDPRESET, 0x4a4)\n+ FIELD(SD1_HSPDPRESET, SD1_HSPDPRESET, 0, 13)\n+REG32(SD1_SDR12PRESET, 0x4a8)\n+ FIELD(SD1_SDR12PRESET, SD1_SDR12PRESET, 0, 13)\n+REG32(SD1_SDR25PRESET, 0x4ac)\n+ FIELD(SD1_SDR25PRESET, SD1_SDR25PRESET, 0, 13)\n+REG32(SD1_SDR50PRSET, 0x4b0)\n+ FIELD(SD1_SDR50PRSET, SD1_SDR50PRESET, 0, 13)\n+REG32(SD1_SDR104PRST, 0x4b4)\n+ FIELD(SD1_SDR104PRST, SD1_SDR104PRESET, 0, 13)\n+REG32(SD1_DDR50PRESET, 0x4b8)\n+ FIELD(SD1_DDR50PRESET, SD1_DDR50PRESET, 0, 13)\n+REG32(SD1_MAXCUR1P8, 0x4bc)\n+ FIELD(SD1_MAXCUR1P8, SD1_MAXCUR1P8, 0, 8)\n+REG32(SD1_MAXCUR3P0, 0x4c0)\n+ FIELD(SD1_MAXCUR3P0, SD1_MAXCUR3P0, 0, 8)\n+REG32(SD1_MAXCUR3P3, 0x4c4)\n+ FIELD(SD1_MAXCUR3P3, SD1_MAXCUR3P3, 0, 8)\n+REG32(SD1_DLL_CTRL, 0x4c8)\n+ FIELD(SD1_DLL_CTRL, SD1_CLKSTABLE_CFG, 9, 1)\n+ FIELD(SD1_DLL_CTRL, SD1_DLL_CFG, 5, 4)\n+ FIELD(SD1_DLL_CTRL, SD1_DLL_PSDONE, 4, 1)\n+ FIELD(SD1_DLL_CTRL, SD1_DLL_OVF, 3, 1)\n+ FIELD(SD1_DLL_CTRL, SD1_DLL_RST, 2, 1)\n+ FIELD(SD1_DLL_CTRL, SD1_DLL_TESTMODE, 1, 1)\n+ FIELD(SD1_DLL_CTRL, SD1_DLL_LOCK, 0, 1)\n+REG32(SD1_CDN_CTRL, 0x4cc)\n+ FIELD(SD1_CDN_CTRL, SD1_CDN_CTRL, 0, 1)\n+REG32(SD1_DLL_TEST, 0x4d0)\n+ FIELD(SD1_DLL_TEST, DLL_DIV, 16, 8)\n+ FIELD(SD1_DLL_TEST, DLL_TX_SEL, 9, 7)\n+ FIELD(SD1_DLL_TEST, DLL_RX_SEL, 0, 9)\n+REG32(SD1_RX_TUNING_SEL, 0x4d4)\n+ FIELD(SD1_RX_TUNING_SEL, SD1_RX_SEL, 0, 9)\n+REG32(SD1_DLL_DIV_MAP0, 0x4d8)\n+ FIELD(SD1_DLL_DIV_MAP0, DIV_3, 24, 8)\n+ FIELD(SD1_DLL_DIV_MAP0, DIV_2, 16, 8)\n+ FIELD(SD1_DLL_DIV_MAP0, DIV_1, 8, 8)\n+ FIELD(SD1_DLL_DIV_MAP0, DIV_0, 0, 8)\n+REG32(SD1_DLL_DIV_MAP1, 0x4dc)\n+ FIELD(SD1_DLL_DIV_MAP1, DIV_7, 24, 8)\n+ FIELD(SD1_DLL_DIV_MAP1, DIV_6, 16, 8)\n+ FIELD(SD1_DLL_DIV_MAP1, DIV_5, 8, 8)\n+ FIELD(SD1_DLL_DIV_MAP1, DIV_4, 0, 8)\n+REG32(SD1_IOU_COHERENT_CTRL, 0x4e0)\n+ FIELD(SD1_IOU_COHERENT_CTRL, SD1_AXI_COH, 0, 4)\n+REG32(SD1_IOU_INTERCONNECT_ROUTE, 0x4e4)\n+ FIELD(SD1_IOU_INTERCONNECT_ROUTE, SD1, 0, 1)\n+REG32(SD1_IOU_RAM, 0x4e8)\n+ FIELD(SD1_IOU_RAM, EMASA0, 6, 1)\n+ FIELD(SD1_IOU_RAM, EMAB0, 3, 3)\n+ FIELD(SD1_IOU_RAM, EMAA0, 0, 3)\n+REG32(SD1_IOU_INTERCONNECT_QOS, 0x4ec)\n+ FIELD(SD1_IOU_INTERCONNECT_QOS, SD1_QOS, 0, 4)\n+REG32(OSPI_QSPI_IOU_AXI_MUX_SEL, 0x504)\n+ FIELD(OSPI_QSPI_IOU_AXI_MUX_SEL, OSPI_MUX_SEL, 1, 1)\n+ FIELD(OSPI_QSPI_IOU_AXI_MUX_SEL, QSPI_OSPI_MUX_SEL, 0, 1)\n+REG32(QSPI_IOU_COHERENT_CTRL, 0x508)\n+ FIELD(QSPI_IOU_COHERENT_CTRL, QSPI_AXI_COH, 0, 4)\n+REG32(QSPI_IOU_INTERCONNECT_ROUTE, 0x50c)\n+ FIELD(QSPI_IOU_INTERCONNECT_ROUTE, QSPI, 0, 1)\n+REG32(QSPI_IOU_RAM, 0x510)\n+ FIELD(QSPI_IOU_RAM, EMASA1, 13, 1)\n+ FIELD(QSPI_IOU_RAM, EMAB1, 10, 3)\n+ FIELD(QSPI_IOU_RAM, EMAA1, 7, 3)\n+ FIELD(QSPI_IOU_RAM, EMASA0, 6, 1)\n+ FIELD(QSPI_IOU_RAM, EMAB0, 3, 3)\n+ FIELD(QSPI_IOU_RAM, EMAA0, 0, 3)\n+REG32(QSPI_IOU_INTERCONNECT_QOS, 0x514)\n+ FIELD(QSPI_IOU_INTERCONNECT_QOS, QSPI_QOS, 0, 4)\n+REG32(OSPI_IOU_COHERENT_CTRL, 0x530)\n+ FIELD(OSPI_IOU_COHERENT_CTRL, OSPI_AXI_COH, 0, 4)\n+REG32(OSPI_IOU_INTERCONNECT_ROUTE, 0x534)\n+ FIELD(OSPI_IOU_INTERCONNECT_ROUTE, OSPI, 0, 1)\n+REG32(OSPI_IOU_RAM, 0x538)\n+ FIELD(OSPI_IOU_RAM, EMAS0, 5, 1)\n+ FIELD(OSPI_IOU_RAM, EMAW0, 3, 2)\n+ FIELD(OSPI_IOU_RAM, EMA0, 0, 3)\n+REG32(OSPI_IOU_INTERCONNECT_QOS, 0x53c)\n+ FIELD(OSPI_IOU_INTERCONNECT_QOS, OSPI_QOS, 0, 4)\n+REG32(OSPI_REFCLK_DLY_CTRL, 0x540)\n+ FIELD(OSPI_REFCLK_DLY_CTRL, DLY1, 3, 2)\n+ FIELD(OSPI_REFCLK_DLY_CTRL, DLY0, 0, 3)\n+REG32(CUR_PWR_ST, 0x600)\n+ FIELD(CUR_PWR_ST, U2PMU, 0, 2)\n+REG32(CONNECT_ST, 0x604)\n+ FIELD(CONNECT_ST, U2PMU, 0, 1)\n+REG32(PW_STATE_REQ, 0x608)\n+ FIELD(PW_STATE_REQ, BIT_1_0, 0, 2)\n+REG32(HOST_U2_PORT_DISABLE, 0x60c)\n+ FIELD(HOST_U2_PORT_DISABLE, BIT_0, 0, 1)\n+REG32(DBG_U2PMU, 0x610)\n+REG32(DBG_U2PMU_EXT1, 0x614)\n+REG32(DBG_U2PMU_EXT2, 0x618)\n+ FIELD(DBG_U2PMU_EXT2, BIT_67_64, 0, 4)\n+REG32(PME_GEN_U2PMU, 0x61c)\n+ FIELD(PME_GEN_U2PMU, BIT_0, 0, 1)\n+REG32(PWR_CONFIG_USB2, 0x620)\n+ FIELD(PWR_CONFIG_USB2, STRAP, 0, 30)\n+REG32(PHY_HUB, 0x624)\n+ FIELD(PHY_HUB, VBUS_CTRL, 1, 1)\n+ FIELD(PHY_HUB, OVER_CURRENT, 0, 1)\n+REG32(CTRL, 0x700)\n+ FIELD(CTRL, SLVERR_ENABLE, 0, 1)\n+REG32(ISR, 0x800)\n+ FIELD(ISR, ADDR_DECODE_ERR, 0, 1)\n+REG32(IMR, 0x804)\n+ FIELD(IMR, ADDR_DECODE_ERR, 0, 1)\n+REG32(IER, 0x808)\n+ FIELD(IER, ADDR_DECODE_ERR, 0, 1)\n+REG32(IDR, 0x80c)\n+ FIELD(IDR, ADDR_DECODE_ERR, 0, 1)\n+REG32(ITR, 0x810)\n+ FIELD(ITR, ADDR_DECODE_ERR, 0, 1)\n+REG32(PARITY_ISR, 0x814)\n+ FIELD(PARITY_ISR, PERR_AXI_SD1_IOU, 12, 1)\n+ FIELD(PARITY_ISR, PERR_AXI_SD0_IOU, 11, 1)\n+ FIELD(PARITY_ISR, PERR_AXI_QSPI_IOU, 10, 1)\n+ FIELD(PARITY_ISR, PERR_AXI_OSPI_IOU, 9, 1)\n+ FIELD(PARITY_ISR, PERR_IOU_SD1, 8, 1)\n+ FIELD(PARITY_ISR, PERR_IOU_SD0, 7, 1)\n+ FIELD(PARITY_ISR, PERR_IOU_QSPI1, 6, 1)\n+ FIELD(PARITY_ISR, PERR_IOUSLCR_SECURE_APB, 5, 1)\n+ FIELD(PARITY_ISR, PERR_IOUSLCR_APB, 4, 1)\n+ FIELD(PARITY_ISR, PERR_QSPI0_APB, 3, 1)\n+ FIELD(PARITY_ISR, PERR_OSPI_APB, 2, 1)\n+ FIELD(PARITY_ISR, PERR_I2C_APB, 1, 1)\n+ FIELD(PARITY_ISR, PERR_GPIO_APB, 0, 1)\n+REG32(PARITY_IMR, 0x818)\n+ FIELD(PARITY_IMR, PERR_AXI_SD1_IOU, 12, 1)\n+ FIELD(PARITY_IMR, PERR_AXI_SD0_IOU, 11, 1)\n+ FIELD(PARITY_IMR, PERR_AXI_QSPI_IOU, 10, 1)\n+ FIELD(PARITY_IMR, PERR_AXI_OSPI_IOU, 9, 1)\n+ FIELD(PARITY_IMR, PERR_IOU_SD1, 8, 1)\n+ FIELD(PARITY_IMR, PERR_IOU_SD0, 7, 1)\n+ FIELD(PARITY_IMR, PERR_IOU_QSPI1, 6, 1)\n+ FIELD(PARITY_IMR, PERR_IOUSLCR_SECURE_APB, 5, 1)\n+ FIELD(PARITY_IMR, PERR_IOUSLCR_APB, 4, 1)\n+ FIELD(PARITY_IMR, PERR_QSPI0_APB, 3, 1)\n+ FIELD(PARITY_IMR, PERR_OSPI_APB, 2, 1)\n+ FIELD(PARITY_IMR, PERR_I2C_APB, 1, 1)\n+ FIELD(PARITY_IMR, PERR_GPIO_APB, 0, 1)\n+REG32(PARITY_IER, 0x81c)\n+ FIELD(PARITY_IER, PERR_AXI_SD1_IOU, 12, 1)\n+ FIELD(PARITY_IER, PERR_AXI_SD0_IOU, 11, 1)\n+ FIELD(PARITY_IER, PERR_AXI_QSPI_IOU, 10, 1)\n+ FIELD(PARITY_IER, PERR_AXI_OSPI_IOU, 9, 1)\n+ FIELD(PARITY_IER, PERR_IOU_SD1, 8, 1)\n+ FIELD(PARITY_IER, PERR_IOU_SD0, 7, 1)\n+ FIELD(PARITY_IER, PERR_IOU_QSPI1, 6, 1)\n+ FIELD(PARITY_IER, PERR_IOUSLCR_SECURE_APB, 5, 1)\n+ FIELD(PARITY_IER, PERR_IOUSLCR_APB, 4, 1)\n+ FIELD(PARITY_IER, PERR_QSPI0_APB, 3, 1)\n+ FIELD(PARITY_IER, PERR_OSPI_APB, 2, 1)\n+ FIELD(PARITY_IER, PERR_I2C_APB, 1, 1)\n+ FIELD(PARITY_IER, PERR_GPIO_APB, 0, 1)\n+REG32(PARITY_IDR, 0x820)\n+ FIELD(PARITY_IDR, PERR_AXI_SD1_IOU, 12, 1)\n+ FIELD(PARITY_IDR, PERR_AXI_SD0_IOU, 11, 1)\n+ FIELD(PARITY_IDR, PERR_AXI_QSPI_IOU, 10, 1)\n+ FIELD(PARITY_IDR, PERR_AXI_OSPI_IOU, 9, 1)\n+ FIELD(PARITY_IDR, PERR_IOU_SD1, 8, 1)\n+ FIELD(PARITY_IDR, PERR_IOU_SD0, 7, 1)\n+ FIELD(PARITY_IDR, PERR_IOU_QSPI1, 6, 1)\n+ FIELD(PARITY_IDR, PERR_IOUSLCR_SECURE_APB, 5, 1)\n+ FIELD(PARITY_IDR, PERR_IOUSLCR_APB, 4, 1)\n+ FIELD(PARITY_IDR, PERR_QSPI0_APB, 3, 1)\n+ FIELD(PARITY_IDR, PERR_OSPI_APB, 2, 1)\n+ FIELD(PARITY_IDR, PERR_I2C_APB, 1, 1)\n+ FIELD(PARITY_IDR, PERR_GPIO_APB, 0, 1)\n+REG32(PARITY_ITR, 0x824)\n+ FIELD(PARITY_ITR, PERR_AXI_SD1_IOU, 12, 1)\n+ FIELD(PARITY_ITR, PERR_AXI_SD0_IOU, 11, 1)\n+ FIELD(PARITY_ITR, PERR_AXI_QSPI_IOU, 10, 1)\n+ FIELD(PARITY_ITR, PERR_AXI_OSPI_IOU, 9, 1)\n+ FIELD(PARITY_ITR, PERR_IOU_SD1, 8, 1)\n+ FIELD(PARITY_ITR, PERR_IOU_SD0, 7, 1)\n+ FIELD(PARITY_ITR, PERR_IOU_QSPI1, 6, 1)\n+ FIELD(PARITY_ITR, PERR_IOUSLCR_SECURE_APB, 5, 1)\n+ FIELD(PARITY_ITR, PERR_IOUSLCR_APB, 4, 1)\n+ FIELD(PARITY_ITR, PERR_QSPI0_APB, 3, 1)\n+ FIELD(PARITY_ITR, PERR_OSPI_APB, 2, 1)\n+ FIELD(PARITY_ITR, PERR_I2C_APB, 1, 1)\n+ FIELD(PARITY_ITR, PERR_GPIO_APB, 0, 1)\n+REG32(WPROT0, 0x828)\n+ FIELD(WPROT0, ACTIVE, 0, 1)\n+\n+static void parity_imr_update_irq(XlnxVersalPmcIouSlcr *s)\n+{\n+ bool pending = s->regs[R_PARITY_ISR] & ~s->regs[R_PARITY_IMR];\n+ qemu_set_irq(s->irq_parity_imr, pending);\n+}\n+\n+static void parity_isr_postw(RegisterInfo *reg, uint64_t val64)\n+{\n+ XlnxVersalPmcIouSlcr *s = XILINX_VERSAL_PMC_IOU_SLCR(reg->opaque);\n+ parity_imr_update_irq(s);\n+}\n+\n+static uint64_t parity_ier_prew(RegisterInfo *reg, uint64_t val64)\n+{\n+ XlnxVersalPmcIouSlcr *s = XILINX_VERSAL_PMC_IOU_SLCR(reg->opaque);\n+ uint32_t val = val64;\n+\n+ s->regs[R_PARITY_IMR] &= ~val;\n+ parity_imr_update_irq(s);\n+ return 0;\n+}\n+\n+static uint64_t parity_idr_prew(RegisterInfo *reg, uint64_t val64)\n+{\n+ XlnxVersalPmcIouSlcr *s = XILINX_VERSAL_PMC_IOU_SLCR(reg->opaque);\n+ uint32_t val = val64;\n+\n+ s->regs[R_PARITY_IMR] |= val;\n+ parity_imr_update_irq(s);\n+ return 0;\n+}\n+\n+static uint64_t parity_itr_prew(RegisterInfo *reg, uint64_t val64)\n+{\n+ XlnxVersalPmcIouSlcr *s = XILINX_VERSAL_PMC_IOU_SLCR(reg->opaque);\n+ uint32_t val = val64;\n+\n+ s->regs[R_PARITY_ISR] |= val;\n+ parity_imr_update_irq(s);\n+ return 0;\n+}\n+\n+static void imr_update_irq(XlnxVersalPmcIouSlcr *s)\n+{\n+ bool pending = s->regs[R_ISR] & ~s->regs[R_IMR];\n+ qemu_set_irq(s->irq_imr, pending);\n+}\n+\n+static void isr_postw(RegisterInfo *reg, uint64_t val64)\n+{\n+ XlnxVersalPmcIouSlcr *s = XILINX_VERSAL_PMC_IOU_SLCR(reg->opaque);\n+ imr_update_irq(s);\n+}\n+\n+static uint64_t ier_prew(RegisterInfo *reg, uint64_t val64)\n+{\n+ XlnxVersalPmcIouSlcr *s = XILINX_VERSAL_PMC_IOU_SLCR(reg->opaque);\n+ uint32_t val = val64;\n+\n+ s->regs[R_IMR] &= ~val;\n+ imr_update_irq(s);\n+ return 0;\n+}\n+\n+static uint64_t idr_prew(RegisterInfo *reg, uint64_t val64)\n+{\n+ XlnxVersalPmcIouSlcr *s = XILINX_VERSAL_PMC_IOU_SLCR(reg->opaque);\n+ uint32_t val = val64;\n+\n+ s->regs[R_IMR] |= val;\n+ imr_update_irq(s);\n+ return 0;\n+}\n+\n+static uint64_t itr_prew(RegisterInfo *reg, uint64_t val64)\n+{\n+ XlnxVersalPmcIouSlcr *s = XILINX_VERSAL_PMC_IOU_SLCR(reg->opaque);\n+ uint32_t val = val64;\n+\n+ s->regs[R_ISR] |= val;\n+ imr_update_irq(s);\n+ return 0;\n+}\n+\n+static uint64_t sd0_ctrl_reg_prew(RegisterInfo *reg, uint64_t val64)\n+{\n+ XlnxVersalPmcIouSlcr *s = XILINX_VERSAL_PMC_IOU_SLCR(reg->opaque);\n+ uint32_t prev = ARRAY_FIELD_EX32(s->regs, SD0_CTRL_REG, SD0_EMMC_SEL);\n+\n+ if (prev != (val64 & R_SD0_CTRL_REG_SD0_EMMC_SEL_MASK)) {\n+ qemu_set_irq(s->sd_emmc_sel[0], !!val64);\n+ }\n+\n+ return val64;\n+}\n+\n+static uint64_t sd1_ctrl_reg_prew(RegisterInfo *reg, uint64_t val64)\n+{\n+ XlnxVersalPmcIouSlcr *s = XILINX_VERSAL_PMC_IOU_SLCR(reg->opaque);\n+ uint32_t prev = ARRAY_FIELD_EX32(s->regs, SD1_CTRL_REG, SD1_EMMC_SEL);\n+\n+ if (prev != (val64 & R_SD1_CTRL_REG_SD1_EMMC_SEL_MASK)) {\n+ qemu_set_irq(s->sd_emmc_sel[1], !!val64);\n+ }\n+\n+ return val64;\n+}\n+\n+static uint64_t ospi_qspi_iou_axi_mux_sel_prew(RegisterInfo *reg,\n+ uint64_t val64)\n+{\n+ XlnxVersalPmcIouSlcr *s = XILINX_VERSAL_PMC_IOU_SLCR(reg->opaque);\n+ uint32_t val32 = (uint32_t) val64;\n+ uint8_t ospi_mux_sel = FIELD_EX32(val32, OSPI_QSPI_IOU_AXI_MUX_SEL,\n+ OSPI_MUX_SEL);\n+ uint8_t qspi_ospi_mux_sel = FIELD_EX32(val32, OSPI_QSPI_IOU_AXI_MUX_SEL,\n+ QSPI_OSPI_MUX_SEL);\n+\n+ if (ospi_mux_sel !=\n+ ARRAY_FIELD_EX32(s->regs, OSPI_QSPI_IOU_AXI_MUX_SEL, OSPI_MUX_SEL)) {\n+ qemu_set_irq(s->ospi_mux_sel, !!ospi_mux_sel);\n+ }\n+\n+ if (qspi_ospi_mux_sel !=\n+ ARRAY_FIELD_EX32(s->regs, OSPI_QSPI_IOU_AXI_MUX_SEL,\n+ QSPI_OSPI_MUX_SEL)) {\n+ qemu_set_irq(s->qspi_ospi_mux_sel, !!qspi_ospi_mux_sel);\n+ }\n+\n+ return val64;\n+}\n+\n+static RegisterAccessInfo pmc_iou_slcr_regs_info[] = {\n+ { .name = \"MIO_PIN_0\", .addr = A_MIO_PIN_0,\n+ .rsvd = 0xfffffc01,\n+ },{ .name = \"MIO_PIN_1\", .addr = A_MIO_PIN_1,\n+ .rsvd = 0xfffffc01,\n+ },{ .name = \"MIO_PIN_2\", .addr = A_MIO_PIN_2,\n+ .rsvd = 0xfffffc01,\n+ },{ .name = \"MIO_PIN_3\", .addr = A_MIO_PIN_3,\n+ .rsvd = 0xfffffc01,\n+ },{ .name = \"MIO_PIN_4\", .addr = A_MIO_PIN_4,\n+ .rsvd = 0xfffffc01,\n+ },{ .name = \"MIO_PIN_5\", .addr = A_MIO_PIN_5,\n+ .rsvd = 0xfffffc01,\n+ },{ .name = \"MIO_PIN_6\", .addr = A_MIO_PIN_6,\n+ .rsvd = 0xfffffc01,\n+ },{ .name = \"MIO_PIN_7\", .addr = A_MIO_PIN_7,\n+ .rsvd = 0xfffffc01,\n+ },{ .name = \"MIO_PIN_8\", .addr = A_MIO_PIN_8,\n+ .rsvd = 0xfffffc01,\n+ },{ .name = \"MIO_PIN_9\", .addr = A_MIO_PIN_9,\n+ .rsvd = 0xfffffc01,\n+ },{ .name = \"MIO_PIN_10\", .addr = A_MIO_PIN_10,\n+ .rsvd = 0xfffffc01,\n+ },{ .name = \"MIO_PIN_11\", .addr = A_MIO_PIN_11,\n+ .rsvd = 0xfffffc01,\n+ },{ .name = \"MIO_PIN_12\", .addr = A_MIO_PIN_12,\n+ .rsvd = 0xfffffc01,\n+ },{ .name = \"MIO_PIN_13\", .addr = A_MIO_PIN_13,\n+ .rsvd = 0xfffffc01,\n+ },{ .name = \"MIO_PIN_14\", .addr = A_MIO_PIN_14,\n+ .rsvd = 0xfffffc01,\n+ },{ .name = \"MIO_PIN_15\", .addr = A_MIO_PIN_15,\n+ .rsvd = 0xfffffc01,\n+ },{ .name = \"MIO_PIN_16\", .addr = A_MIO_PIN_16,\n+ .rsvd = 0xfffffc01,\n+ },{ .name = \"MIO_PIN_17\", .addr = A_MIO_PIN_17,\n+ .rsvd = 0xfffffc01,\n+ },{ .name = \"MIO_PIN_18\", .addr = A_MIO_PIN_18,\n+ .rsvd = 0xfffffc01,\n+ },{ .name = \"MIO_PIN_19\", .addr = A_MIO_PIN_19,\n+ .rsvd = 0xfffffc01,\n+ },{ .name = \"MIO_PIN_20\", .addr = A_MIO_PIN_20,\n+ .rsvd = 0xfffffc01,\n+ },{ .name = \"MIO_PIN_21\", .addr = A_MIO_PIN_21,\n+ .rsvd = 0xfffffc01,\n+ },{ .name = \"MIO_PIN_22\", .addr = A_MIO_PIN_22,\n+ .rsvd = 0xfffffc01,\n+ },{ .name = \"MIO_PIN_23\", .addr = A_MIO_PIN_23,\n+ .rsvd = 0xfffffc01,\n+ },{ .name = \"MIO_PIN_24\", .addr = A_MIO_PIN_24,\n+ .rsvd = 0xfffffc01,\n+ },{ .name = \"MIO_PIN_25\", .addr = A_MIO_PIN_25,\n+ .rsvd = 0xfffffc01,\n+ },{ .name = \"MIO_PIN_26\", .addr = A_MIO_PIN_26,\n+ .rsvd = 0xfffffc01,\n+ },{ .name = \"MIO_PIN_27\", .addr = A_MIO_PIN_27,\n+ .rsvd = 0xfffffc01,\n+ },{ .name = \"MIO_PIN_28\", .addr = A_MIO_PIN_28,\n+ .rsvd = 0xfffffc01,\n+ },{ .name = \"MIO_PIN_29\", .addr = A_MIO_PIN_29,\n+ .rsvd = 0xfffffc01,\n+ },{ .name = \"MIO_PIN_30\", .addr = A_MIO_PIN_30,\n+ .rsvd = 0xfffffc01,\n+ },{ .name = \"MIO_PIN_31\", .addr = A_MIO_PIN_31,\n+ .rsvd = 0xfffffc01,\n+ },{ .name = \"MIO_PIN_32\", .addr = A_MIO_PIN_32,\n+ .rsvd = 0xfffffc01,\n+ },{ .name = \"MIO_PIN_33\", .addr = A_MIO_PIN_33,\n+ .rsvd = 0xfffffc01,\n+ },{ .name = \"MIO_PIN_34\", .addr = A_MIO_PIN_34,\n+ .rsvd = 0xfffffc01,\n+ },{ .name = \"MIO_PIN_35\", .addr = A_MIO_PIN_35,\n+ .rsvd = 0xfffffc01,\n+ },{ .name = \"MIO_PIN_36\", .addr = A_MIO_PIN_36,\n+ .rsvd = 0xfffffc01,\n+ },{ .name = \"MIO_PIN_37\", .addr = A_MIO_PIN_37,\n+ .rsvd = 0xfffffc01,\n+ },{ .name = \"MIO_PIN_38\", .addr = A_MIO_PIN_38,\n+ .rsvd = 0xfffffc01,\n+ },{ .name = \"MIO_PIN_39\", .addr = A_MIO_PIN_39,\n+ .rsvd = 0xfffffc01,\n+ },{ .name = \"MIO_PIN_40\", .addr = A_MIO_PIN_40,\n+ .rsvd = 0xfffffc01,\n+ },{ .name = \"MIO_PIN_41\", .addr = A_MIO_PIN_41,\n+ .rsvd = 0xfffffc01,\n+ },{ .name = \"MIO_PIN_42\", .addr = A_MIO_PIN_42,\n+ .rsvd = 0xfffffc01,\n+ },{ .name = \"MIO_PIN_43\", .addr = A_MIO_PIN_43,\n+ .rsvd = 0xfffffc01,\n+ },{ .name = \"MIO_PIN_44\", .addr = A_MIO_PIN_44,\n+ .rsvd = 0xfffffc01,\n+ },{ .name = \"MIO_PIN_45\", .addr = A_MIO_PIN_45,\n+ .rsvd = 0xfffffc01,\n+ },{ .name = \"MIO_PIN_46\", .addr = A_MIO_PIN_46,\n+ .rsvd = 0xfffffc01,\n+ },{ .name = \"MIO_PIN_47\", .addr = A_MIO_PIN_47,\n+ .rsvd = 0xfffffc01,\n+ },{ .name = \"MIO_PIN_48\", .addr = A_MIO_PIN_48,\n+ .rsvd = 0xfffffc01,\n+ },{ .name = \"MIO_PIN_49\", .addr = A_MIO_PIN_49,\n+ .rsvd = 0xfffffc01,\n+ },{ .name = \"MIO_PIN_50\", .addr = A_MIO_PIN_50,\n+ .rsvd = 0xfffffc01,\n+ },{ .name = \"MIO_PIN_51\", .addr = A_MIO_PIN_51,\n+ .rsvd = 0xfffffc01,\n+ },{ .name = \"BNK0_EN_RX\", .addr = A_BNK0_EN_RX,\n+ .reset = 0x3ffffff,\n+ .rsvd = 0xfc000000,\n+ },{ .name = \"BNK0_SEL_RX0\", .addr = A_BNK0_SEL_RX0,\n+ .reset = 0xffffffff,\n+ },{ .name = \"BNK0_SEL_RX1\", .addr = A_BNK0_SEL_RX1,\n+ .reset = 0xfffff,\n+ .rsvd = 0xfff00000,\n+ },{ .name = \"BNK0_EN_RX_SCHMITT_HYST\", .addr = A_BNK0_EN_RX_SCHMITT_HYST,\n+ .rsvd = 0xfc000000,\n+ },{ .name = \"BNK0_EN_WK_PD\", .addr = A_BNK0_EN_WK_PD,\n+ .rsvd = 0xfc000000,\n+ },{ .name = \"BNK0_EN_WK_PU\", .addr = A_BNK0_EN_WK_PU,\n+ .reset = 0x3ffffff,\n+ .rsvd = 0xfc000000,\n+ },{ .name = \"BNK0_SEL_DRV0\", .addr = A_BNK0_SEL_DRV0,\n+ .reset = 0xffffffff,\n+ },{ .name = \"BNK0_SEL_DRV1\", .addr = A_BNK0_SEL_DRV1,\n+ .reset = 0xfffff,\n+ .rsvd = 0xfff00000,\n+ },{ .name = \"BNK0_SEL_SLEW\", .addr = A_BNK0_SEL_SLEW,\n+ .rsvd = 0xfc000000,\n+ },{ .name = \"BNK0_EN_DFT_OPT_INV\", .addr = A_BNK0_EN_DFT_OPT_INV,\n+ .rsvd = 0xfc000000,\n+ },{ .name = \"BNK0_EN_PAD2PAD_LOOPBACK\",\n+ .addr = A_BNK0_EN_PAD2PAD_LOOPBACK,\n+ .rsvd = 0xffffe000,\n+ },{ .name = \"BNK0_RX_SPARE0\", .addr = A_BNK0_RX_SPARE0,\n+ },{ .name = \"BNK0_RX_SPARE1\", .addr = A_BNK0_RX_SPARE1,\n+ .rsvd = 0xfff00000,\n+ },{ .name = \"BNK0_TX_SPARE0\", .addr = A_BNK0_TX_SPARE0,\n+ },{ .name = \"BNK0_TX_SPARE1\", .addr = A_BNK0_TX_SPARE1,\n+ .rsvd = 0xfff00000,\n+ },{ .name = \"BNK0_SEL_EN1P8\", .addr = A_BNK0_SEL_EN1P8,\n+ .rsvd = 0xfffffffe,\n+ },{ .name = \"BNK0_EN_B_POR_DETECT\", .addr = A_BNK0_EN_B_POR_DETECT,\n+ .rsvd = 0xfffffffe,\n+ },{ .name = \"BNK0_LPF_BYP_POR_DETECT\", .addr = A_BNK0_LPF_BYP_POR_DETECT,\n+ .reset = 0x1,\n+ .rsvd = 0xfffffffe,\n+ },{ .name = \"BNK0_EN_LATCH\", .addr = A_BNK0_EN_LATCH,\n+ .rsvd = 0xfffffffe,\n+ },{ .name = \"BNK0_VBG_LPF_BYP_B\", .addr = A_BNK0_VBG_LPF_BYP_B,\n+ .reset = 0x1,\n+ .rsvd = 0xfffffffe,\n+ },{ .name = \"BNK0_EN_AMP_B\", .addr = A_BNK0_EN_AMP_B,\n+ .rsvd = 0xfffffffc,\n+ },{ .name = \"BNK0_SPARE_BIAS\", .addr = A_BNK0_SPARE_BIAS,\n+ .rsvd = 0xfffffff0,\n+ },{ .name = \"BNK0_DRIVER_BIAS\", .addr = A_BNK0_DRIVER_BIAS,\n+ .rsvd = 0xffff8000,\n+ },{ .name = \"BNK0_VMODE\", .addr = A_BNK0_VMODE,\n+ .rsvd = 0xfffffffe,\n+ .ro = 0x1,\n+ },{ .name = \"BNK0_SEL_AUX_IO_RX\", .addr = A_BNK0_SEL_AUX_IO_RX,\n+ .rsvd = 0xfc000000,\n+ },{ .name = \"BNK0_EN_TX_HS_MODE\", .addr = A_BNK0_EN_TX_HS_MODE,\n+ .rsvd = 0xfc000000,\n+ },{ .name = \"MIO_MST_TRI0\", .addr = A_MIO_MST_TRI0,\n+ .reset = 0x3ffffff,\n+ .rsvd = 0xfc000000,\n+ },{ .name = \"MIO_MST_TRI1\", .addr = A_MIO_MST_TRI1,\n+ .reset = 0x3ffffff,\n+ .rsvd = 0xfc000000,\n+ },{ .name = \"BNK1_EN_RX\", .addr = A_BNK1_EN_RX,\n+ .reset = 0x3ffffff,\n+ .rsvd = 0xfc000000,\n+ },{ .name = \"BNK1_SEL_RX0\", .addr = A_BNK1_SEL_RX0,\n+ .reset = 0xffffffff,\n+ },{ .name = \"BNK1_SEL_RX1\", .addr = A_BNK1_SEL_RX1,\n+ .reset = 0xfffff,\n+ .rsvd = 0xfff00000,\n+ },{ .name = \"BNK1_EN_RX_SCHMITT_HYST\", .addr = A_BNK1_EN_RX_SCHMITT_HYST,\n+ .rsvd = 0xfc000000,\n+ },{ .name = \"BNK1_EN_WK_PD\", .addr = A_BNK1_EN_WK_PD,\n+ .rsvd = 0xfc000000,\n+ },{ .name = \"BNK1_EN_WK_PU\", .addr = A_BNK1_EN_WK_PU,\n+ .reset = 0x3ffffff,\n+ .rsvd = 0xfc000000,\n+ },{ .name = \"BNK1_SEL_DRV0\", .addr = A_BNK1_SEL_DRV0,\n+ .reset = 0xffffffff,\n+ },{ .name = \"BNK1_SEL_DRV1\", .addr = A_BNK1_SEL_DRV1,\n+ .reset = 0xfffff,\n+ .rsvd = 0xfff00000,\n+ },{ .name = \"BNK1_SEL_SLEW\", .addr = A_BNK1_SEL_SLEW,\n+ .rsvd = 0xfc000000,\n+ },{ .name = \"BNK1_EN_DFT_OPT_INV\", .addr = A_BNK1_EN_DFT_OPT_INV,\n+ .rsvd = 0xfc000000,\n+ },{ .name = \"BNK1_EN_PAD2PAD_LOOPBACK\",\n+ .addr = A_BNK1_EN_PAD2PAD_LOOPBACK,\n+ .rsvd = 0xffffe000,\n+ },{ .name = \"BNK1_RX_SPARE0\", .addr = A_BNK1_RX_SPARE0,\n+ },{ .name = \"BNK1_RX_SPARE1\", .addr = A_BNK1_RX_SPARE1,\n+ .rsvd = 0xfff00000,\n+ },{ .name = \"BNK1_TX_SPARE0\", .addr = A_BNK1_TX_SPARE0,\n+ },{ .name = \"BNK1_TX_SPARE1\", .addr = A_BNK1_TX_SPARE1,\n+ .rsvd = 0xfff00000,\n+ },{ .name = \"BNK1_SEL_EN1P8\", .addr = A_BNK1_SEL_EN1P8,\n+ .rsvd = 0xfffffffe,\n+ },{ .name = \"BNK1_EN_B_POR_DETECT\", .addr = A_BNK1_EN_B_POR_DETECT,\n+ .rsvd = 0xfffffffe,\n+ },{ .name = \"BNK1_LPF_BYP_POR_DETECT\", .addr = A_BNK1_LPF_BYP_POR_DETECT,\n+ .reset = 0x1,\n+ .rsvd = 0xfffffffe,\n+ },{ .name = \"BNK1_EN_LATCH\", .addr = A_BNK1_EN_LATCH,\n+ .rsvd = 0xfffffffe,\n+ },{ .name = \"BNK1_VBG_LPF_BYP_B\", .addr = A_BNK1_VBG_LPF_BYP_B,\n+ .reset = 0x1,\n+ .rsvd = 0xfffffffe,\n+ },{ .name = \"BNK1_EN_AMP_B\", .addr = A_BNK1_EN_AMP_B,\n+ .rsvd = 0xfffffffc,\n+ },{ .name = \"BNK1_SPARE_BIAS\", .addr = A_BNK1_SPARE_BIAS,\n+ .rsvd = 0xfffffff0,\n+ },{ .name = \"BNK1_DRIVER_BIAS\", .addr = A_BNK1_DRIVER_BIAS,\n+ .rsvd = 0xffff8000,\n+ },{ .name = \"BNK1_VMODE\", .addr = A_BNK1_VMODE,\n+ .rsvd = 0xfffffffe,\n+ .ro = 0x1,\n+ },{ .name = \"BNK1_SEL_AUX_IO_RX\", .addr = A_BNK1_SEL_AUX_IO_RX,\n+ .rsvd = 0xfc000000,\n+ },{ .name = \"BNK1_EN_TX_HS_MODE\", .addr = A_BNK1_EN_TX_HS_MODE,\n+ .rsvd = 0xfc000000,\n+ },{ .name = \"SD0_CLK_CTRL\", .addr = A_SD0_CLK_CTRL,\n+ .rsvd = 0xfffffff8,\n+ },{ .name = \"SD0_CTRL_REG\", .addr = A_SD0_CTRL_REG,\n+ .rsvd = 0xfffffffe,\n+ .pre_write = sd0_ctrl_reg_prew,\n+ },{ .name = \"SD0_CONFIG_REG1\", .addr = A_SD0_CONFIG_REG1,\n+ .reset = 0x3250,\n+ .rsvd = 0xffff8000,\n+ },{ .name = \"SD0_CONFIG_REG2\", .addr = A_SD0_CONFIG_REG2,\n+ .reset = 0xffc,\n+ .rsvd = 0xffffc000,\n+ },{ .name = \"SD0_CONFIG_REG3\", .addr = A_SD0_CONFIG_REG3,\n+ .reset = 0x407,\n+ .rsvd = 0xfffff800,\n+ },{ .name = \"SD0_INITPRESET\", .addr = A_SD0_INITPRESET,\n+ .reset = 0x100,\n+ .rsvd = 0xffffe000,\n+ },{ .name = \"SD0_DSPPRESET\", .addr = A_SD0_DSPPRESET,\n+ .reset = 0x4,\n+ .rsvd = 0xffffe000,\n+ },{ .name = \"SD0_HSPDPRESET\", .addr = A_SD0_HSPDPRESET,\n+ .reset = 0x2,\n+ .rsvd = 0xffffe000,\n+ },{ .name = \"SD0_SDR12PRESET\", .addr = A_SD0_SDR12PRESET,\n+ .reset = 0x4,\n+ .rsvd = 0xffffe000,\n+ },{ .name = \"SD0_SDR25PRESET\", .addr = A_SD0_SDR25PRESET,\n+ .reset = 0x2,\n+ .rsvd = 0xffffe000,\n+ },{ .name = \"SD0_SDR50PRSET\", .addr = A_SD0_SDR50PRSET,\n+ .reset = 0x1,\n+ .rsvd = 0xffffe000,\n+ },{ .name = \"SD0_SDR104PRST\", .addr = A_SD0_SDR104PRST,\n+ .rsvd = 0xffffe000,\n+ },{ .name = \"SD0_DDR50PRESET\", .addr = A_SD0_DDR50PRESET,\n+ .reset = 0x2,\n+ .rsvd = 0xffffe000,\n+ },{ .name = \"SD0_MAXCUR1P8\", .addr = A_SD0_MAXCUR1P8,\n+ .rsvd = 0xffffff00,\n+ },{ .name = \"SD0_MAXCUR3P0\", .addr = A_SD0_MAXCUR3P0,\n+ .rsvd = 0xffffff00,\n+ },{ .name = \"SD0_MAXCUR3P3\", .addr = A_SD0_MAXCUR3P3,\n+ .rsvd = 0xffffff00,\n+ },{ .name = \"SD0_DLL_CTRL\", .addr = A_SD0_DLL_CTRL,\n+ .reset = 0x1,\n+ .rsvd = 0xfffffc00,\n+ .ro = 0x19,\n+ },{ .name = \"SD0_CDN_CTRL\", .addr = A_SD0_CDN_CTRL,\n+ .rsvd = 0xfffffffe,\n+ },{ .name = \"SD0_DLL_TEST\", .addr = A_SD0_DLL_TEST,\n+ .rsvd = 0xff000000,\n+ },{ .name = \"SD0_RX_TUNING_SEL\", .addr = A_SD0_RX_TUNING_SEL,\n+ .rsvd = 0xfffffe00,\n+ .ro = 0x1ff,\n+ },{ .name = \"SD0_DLL_DIV_MAP0\", .addr = A_SD0_DLL_DIV_MAP0,\n+ .reset = 0x50505050,\n+ },{ .name = \"SD0_DLL_DIV_MAP1\", .addr = A_SD0_DLL_DIV_MAP1,\n+ .reset = 0x50505050,\n+ },{ .name = \"SD0_IOU_COHERENT_CTRL\", .addr = A_SD0_IOU_COHERENT_CTRL,\n+ .rsvd = 0xfffffff0,\n+ },{ .name = \"SD0_IOU_INTERCONNECT_ROUTE\",\n+ .addr = A_SD0_IOU_INTERCONNECT_ROUTE,\n+ .rsvd = 0xfffffffe,\n+ },{ .name = \"SD0_IOU_RAM\", .addr = A_SD0_IOU_RAM,\n+ .reset = 0x24,\n+ .rsvd = 0xffffff80,\n+ },{ .name = \"SD0_IOU_INTERCONNECT_QOS\",\n+ .addr = A_SD0_IOU_INTERCONNECT_QOS,\n+ .rsvd = 0xfffffff0,\n+ },{ .name = \"SD1_CLK_CTRL\", .addr = A_SD1_CLK_CTRL,\n+ .rsvd = 0xfffffffc,\n+ },{ .name = \"SD1_CTRL_REG\", .addr = A_SD1_CTRL_REG,\n+ .rsvd = 0xfffffffe,\n+ .pre_write = sd1_ctrl_reg_prew,\n+ },{ .name = \"SD1_CONFIG_REG1\", .addr = A_SD1_CONFIG_REG1,\n+ .reset = 0x3250,\n+ .rsvd = 0xffff8000,\n+ },{ .name = \"SD1_CONFIG_REG2\", .addr = A_SD1_CONFIG_REG2,\n+ .reset = 0xffc,\n+ .rsvd = 0xffffc000,\n+ },{ .name = \"SD1_CONFIG_REG3\", .addr = A_SD1_CONFIG_REG3,\n+ .reset = 0x407,\n+ .rsvd = 0xfffff800,\n+ },{ .name = \"SD1_INITPRESET\", .addr = A_SD1_INITPRESET,\n+ .reset = 0x100,\n+ .rsvd = 0xffffe000,\n+ },{ .name = \"SD1_DSPPRESET\", .addr = A_SD1_DSPPRESET,\n+ .reset = 0x4,\n+ .rsvd = 0xffffe000,\n+ },{ .name = \"SD1_HSPDPRESET\", .addr = A_SD1_HSPDPRESET,\n+ .reset = 0x2,\n+ .rsvd = 0xffffe000,\n+ },{ .name = \"SD1_SDR12PRESET\", .addr = A_SD1_SDR12PRESET,\n+ .reset = 0x4,\n+ .rsvd = 0xffffe000,\n+ },{ .name = \"SD1_SDR25PRESET\", .addr = A_SD1_SDR25PRESET,\n+ .reset = 0x2,\n+ .rsvd = 0xffffe000,\n+ },{ .name = \"SD1_SDR50PRSET\", .addr = A_SD1_SDR50PRSET,\n+ .reset = 0x1,\n+ .rsvd = 0xffffe000,\n+ },{ .name = \"SD1_SDR104PRST\", .addr = A_SD1_SDR104PRST,\n+ .rsvd = 0xffffe000,\n+ },{ .name = \"SD1_DDR50PRESET\", .addr = A_SD1_DDR50PRESET,\n+ .reset = 0x2,\n+ .rsvd = 0xffffe000,\n+ },{ .name = \"SD1_MAXCUR1P8\", .addr = A_SD1_MAXCUR1P8,\n+ .rsvd = 0xffffff00,\n+ },{ .name = \"SD1_MAXCUR3P0\", .addr = A_SD1_MAXCUR3P0,\n+ .rsvd = 0xffffff00,\n+ },{ .name = \"SD1_MAXCUR3P3\", .addr = A_SD1_MAXCUR3P3,\n+ .rsvd = 0xffffff00,\n+ },{ .name = \"SD1_DLL_CTRL\", .addr = A_SD1_DLL_CTRL,\n+ .reset = 0x1,\n+ .rsvd = 0xfffffc00,\n+ .ro = 0x19,\n+ },{ .name = \"SD1_CDN_CTRL\", .addr = A_SD1_CDN_CTRL,\n+ .rsvd = 0xfffffffe,\n+ },{ .name = \"SD1_DLL_TEST\", .addr = A_SD1_DLL_TEST,\n+ .rsvd = 0xff000000,\n+ },{ .name = \"SD1_RX_TUNING_SEL\", .addr = A_SD1_RX_TUNING_SEL,\n+ .rsvd = 0xfffffe00,\n+ .ro = 0x1ff,\n+ },{ .name = \"SD1_DLL_DIV_MAP0\", .addr = A_SD1_DLL_DIV_MAP0,\n+ .reset = 0x50505050,\n+ },{ .name = \"SD1_DLL_DIV_MAP1\", .addr = A_SD1_DLL_DIV_MAP1,\n+ .reset = 0x50505050,\n+ },{ .name = \"SD1_IOU_COHERENT_CTRL\", .addr = A_SD1_IOU_COHERENT_CTRL,\n+ .rsvd = 0xfffffff0,\n+ },{ .name = \"SD1_IOU_INTERCONNECT_ROUTE\",\n+ .addr = A_SD1_IOU_INTERCONNECT_ROUTE,\n+ .rsvd = 0xfffffffe,\n+ },{ .name = \"SD1_IOU_RAM\", .addr = A_SD1_IOU_RAM,\n+ .reset = 0x24,\n+ .rsvd = 0xffffff80,\n+ },{ .name = \"SD1_IOU_INTERCONNECT_QOS\",\n+ .addr = A_SD1_IOU_INTERCONNECT_QOS,\n+ .rsvd = 0xfffffff0,\n+ },{ .name = \"OSPI_QSPI_IOU_AXI_MUX_SEL\",\n+ .addr = A_OSPI_QSPI_IOU_AXI_MUX_SEL,\n+ .reset = 0x1,\n+ .rsvd = 0xfffffffc,\n+ .pre_write = ospi_qspi_iou_axi_mux_sel_prew,\n+ },{ .name = \"QSPI_IOU_COHERENT_CTRL\", .addr = A_QSPI_IOU_COHERENT_CTRL,\n+ .rsvd = 0xfffffff0,\n+ },{ .name = \"QSPI_IOU_INTERCONNECT_ROUTE\",\n+ .addr = A_QSPI_IOU_INTERCONNECT_ROUTE,\n+ .rsvd = 0xfffffffe,\n+ },{ .name = \"QSPI_IOU_RAM\", .addr = A_QSPI_IOU_RAM,\n+ .reset = 0x1224,\n+ .rsvd = 0xffffc000,\n+ },{ .name = \"QSPI_IOU_INTERCONNECT_QOS\",\n+ .addr = A_QSPI_IOU_INTERCONNECT_QOS,\n+ .rsvd = 0xfffffff0,\n+ },{ .name = \"OSPI_IOU_COHERENT_CTRL\", .addr = A_OSPI_IOU_COHERENT_CTRL,\n+ .rsvd = 0xfffffff0,\n+ },{ .name = \"OSPI_IOU_INTERCONNECT_ROUTE\",\n+ .addr = A_OSPI_IOU_INTERCONNECT_ROUTE,\n+ .rsvd = 0xfffffffe,\n+ },{ .name = \"OSPI_IOU_RAM\", .addr = A_OSPI_IOU_RAM,\n+ .reset = 0xa,\n+ .rsvd = 0xffffffc0,\n+ },{ .name = \"OSPI_IOU_INTERCONNECT_QOS\",\n+ .addr = A_OSPI_IOU_INTERCONNECT_QOS,\n+ .rsvd = 0xfffffff0,\n+ },{ .name = \"OSPI_REFCLK_DLY_CTRL\", .addr = A_OSPI_REFCLK_DLY_CTRL,\n+ .reset = 0x13,\n+ .rsvd = 0xffffffe0,\n+ },{ .name = \"CUR_PWR_ST\", .addr = A_CUR_PWR_ST,\n+ .rsvd = 0xfffffffc,\n+ .ro = 0x3,\n+ },{ .name = \"CONNECT_ST\", .addr = A_CONNECT_ST,\n+ .rsvd = 0xfffffffe,\n+ .ro = 0x1,\n+ },{ .name = \"PW_STATE_REQ\", .addr = A_PW_STATE_REQ,\n+ .rsvd = 0xfffffffc,\n+ },{ .name = \"HOST_U2_PORT_DISABLE\", .addr = A_HOST_U2_PORT_DISABLE,\n+ .rsvd = 0xfffffffe,\n+ },{ .name = \"DBG_U2PMU\", .addr = A_DBG_U2PMU,\n+ .ro = 0xffffffff,\n+ },{ .name = \"DBG_U2PMU_EXT1\", .addr = A_DBG_U2PMU_EXT1,\n+ .ro = 0xffffffff,\n+ },{ .name = \"DBG_U2PMU_EXT2\", .addr = A_DBG_U2PMU_EXT2,\n+ .rsvd = 0xfffffff0,\n+ .ro = 0xf,\n+ },{ .name = \"PME_GEN_U2PMU\", .addr = A_PME_GEN_U2PMU,\n+ .rsvd = 0xfffffffe,\n+ .ro = 0x1,\n+ },{ .name = \"PWR_CONFIG_USB2\", .addr = A_PWR_CONFIG_USB2,\n+ .rsvd = 0xc0000000,\n+ },{ .name = \"PHY_HUB\", .addr = A_PHY_HUB,\n+ .rsvd = 0xfffffffc,\n+ .ro = 0x2,\n+ },{ .name = \"CTRL\", .addr = A_CTRL,\n+ },{ .name = \"ISR\", .addr = A_ISR,\n+ .w1c = 0x1,\n+ .post_write = isr_postw,\n+ },{ .name = \"IMR\", .addr = A_IMR,\n+ .reset = 0x1,\n+ .ro = 0x1,\n+ },{ .name = \"IER\", .addr = A_IER,\n+ .pre_write = ier_prew,\n+ },{ .name = \"IDR\", .addr = A_IDR,\n+ .pre_write = idr_prew,\n+ },{ .name = \"ITR\", .addr = A_ITR,\n+ .pre_write = itr_prew,\n+ },{ .name = \"PARITY_ISR\", .addr = A_PARITY_ISR,\n+ .w1c = 0x1fff,\n+ .post_write = parity_isr_postw,\n+ },{ .name = \"PARITY_IMR\", .addr = A_PARITY_IMR,\n+ .reset = 0x1fff,\n+ .ro = 0x1fff,\n+ },{ .name = \"PARITY_IER\", .addr = A_PARITY_IER,\n+ .pre_write = parity_ier_prew,\n+ },{ .name = \"PARITY_IDR\", .addr = A_PARITY_IDR,\n+ .pre_write = parity_idr_prew,\n+ },{ .name = \"PARITY_ITR\", .addr = A_PARITY_ITR,\n+ .pre_write = parity_itr_prew,\n+ },{ .name = \"WPROT0\", .addr = A_WPROT0,\n+ .reset = 0x1,\n+ }\n+};\n+\n+static void xlnx_versal_pmc_iou_slcr_reset_init(Object *obj, ResetType type)\n+{\n+ XlnxVersalPmcIouSlcr *s = XILINX_VERSAL_PMC_IOU_SLCR(obj);\n+ unsigned int i;\n+\n+ for (i = 0; i < ARRAY_SIZE(s->regs_info); ++i) {\n+ register_reset(&s->regs_info[i]);\n+ }\n+}\n+\n+static void xlnx_versal_pmc_iou_slcr_reset_hold(Object *obj)\n+{\n+ XlnxVersalPmcIouSlcr *s = XILINX_VERSAL_PMC_IOU_SLCR(obj);\n+\n+ parity_imr_update_irq(s);\n+ imr_update_irq(s);\n+\n+ /*\n+ * Setup OSPI_QSPI mux\n+ * By default axi slave interface is enabled for ospi-dma\n+ */\n+ qemu_set_irq(s->ospi_mux_sel, 0);\n+ qemu_set_irq(s->qspi_ospi_mux_sel, 1);\n+}\n+\n+static const MemoryRegionOps pmc_iou_slcr_ops = {\n+ .read = register_read_memory,\n+ .write = register_write_memory,\n+ .endianness = DEVICE_LITTLE_ENDIAN,\n+ .valid = {\n+ .min_access_size = 4,\n+ .max_access_size = 4,\n+ },\n+};\n+\n+static void xlnx_versal_pmc_iou_slcr_realize(DeviceState *dev, Error **errp)\n+{\n+ XlnxVersalPmcIouSlcr *s = XILINX_VERSAL_PMC_IOU_SLCR(dev);\n+\n+ qdev_init_gpio_out_named(dev, s->sd_emmc_sel, \"sd-emmc-sel\", 2);\n+ qdev_init_gpio_out_named(dev, &s->qspi_ospi_mux_sel,\n+ \"qspi-ospi-mux-sel\", 1);\n+ qdev_init_gpio_out_named(dev, &s->ospi_mux_sel, \"ospi-mux-sel\", 1);\n+}\n+\n+static void xlnx_versal_pmc_iou_slcr_init(Object *obj)\n+{\n+ XlnxVersalPmcIouSlcr *s = XILINX_VERSAL_PMC_IOU_SLCR(obj);\n+ SysBusDevice *sbd = SYS_BUS_DEVICE(obj);\n+ RegisterInfoArray *reg_array;\n+\n+ memory_region_init(&s->iomem, obj, TYPE_XILINX_VERSAL_PMC_IOU_SLCR,\n+ XILINX_VERSAL_PMC_IOU_SLCR_R_MAX * 4);\n+ reg_array =\n+ register_init_block32(DEVICE(obj), pmc_iou_slcr_regs_info,\n+ ARRAY_SIZE(pmc_iou_slcr_regs_info),\n+ s->regs_info, s->regs,\n+ &pmc_iou_slcr_ops,\n+ XILINX_VERSAL_PMC_IOU_SLCR_ERR_DEBUG,\n+ XILINX_VERSAL_PMC_IOU_SLCR_R_MAX * 4);\n+ memory_region_add_subregion(&s->iomem,\n+ 0x0,\n+ ®_array->mem);\n+ sysbus_init_mmio(sbd, &s->iomem);\n+ sysbus_init_irq(sbd, &s->irq_parity_imr);\n+ sysbus_init_irq(sbd, &s->irq_imr);\n+}\n+\n+static const VMStateDescription vmstate_pmc_iou_slcr = {\n+ .name = TYPE_XILINX_VERSAL_PMC_IOU_SLCR,\n+ .version_id = 1,\n+ .minimum_version_id = 1,\n+ .fields = (VMStateField[]) {\n+ VMSTATE_UINT32_ARRAY(regs, XlnxVersalPmcIouSlcr,\n+ XILINX_VERSAL_PMC_IOU_SLCR_R_MAX),\n+ VMSTATE_END_OF_LIST(),\n+ }\n+};\n+\n+static void xlnx_versal_pmc_iou_slcr_class_init(ObjectClass *klass, void *data)\n+{\n+ DeviceClass *dc = DEVICE_CLASS(klass);\n+ ResettableClass *rc = RESETTABLE_CLASS(klass);\n+\n+ dc->realize = xlnx_versal_pmc_iou_slcr_realize;\n+ dc->vmsd = &vmstate_pmc_iou_slcr;\n+ rc->phases.enter = xlnx_versal_pmc_iou_slcr_reset_init;\n+ rc->phases.hold = xlnx_versal_pmc_iou_slcr_reset_hold;\n+}\n+\n+static const TypeInfo xlnx_versal_pmc_iou_slcr_info = {\n+ .name = TYPE_XILINX_VERSAL_PMC_IOU_SLCR,\n+ .parent = TYPE_SYS_BUS_DEVICE,\n+ .instance_size = sizeof(XlnxVersalPmcIouSlcr),\n+ .class_init = xlnx_versal_pmc_iou_slcr_class_init,\n+ .instance_init = xlnx_versal_pmc_iou_slcr_init,\n+};\n+\n+static void xlnx_versal_pmc_iou_slcr_register_types(void)\n+{\n+ type_register_static(&xlnx_versal_pmc_iou_slcr_info);\n+}\n+\n+type_init(xlnx_versal_pmc_iou_slcr_register_types)\ndiff --git a/hw/misc/meson.build b/hw/misc/meson.build\nindex d1a11691087..6dcbe044f3f 100644\n--- a/hw/misc/meson.build\n+++ b/hw/misc/meson.build\n@@ -84,7 +84,10 @@ softmmu_ss.add(when: 'CONFIG_RASPI', if_true: files(\n ))\n softmmu_ss.add(when: 'CONFIG_SLAVIO', if_true: files('slavio_misc.c'))\n softmmu_ss.add(when: 'CONFIG_ZYNQ', if_true: files('zynq_slcr.c'))\n-softmmu_ss.add(when: 'CONFIG_XLNX_VERSAL', if_true: files('xlnx-versal-xramc.c'))\n+softmmu_ss.add(when: 'CONFIG_XLNX_VERSAL', if_true: files(\n+ 'xlnx-versal-xramc.c',\n+ 'xlnx-versal-pmc-iou-slcr.c',\n+))\n softmmu_ss.add(when: 'CONFIG_STM32F2XX_SYSCFG', if_true: files('stm32f2xx_syscfg.c'))\n softmmu_ss.add(when: 'CONFIG_STM32F4XX_SYSCFG', if_true: files('stm32f4xx_syscfg.c'))\n softmmu_ss.add(when: 'CONFIG_STM32F4XX_EXTI', if_true: files('stm32f4xx_exti.c'))\n","prefixes":["PULL","05/32"]}