{"id":1585796,"url":"http://patchwork.ozlabs.org/api/patches/1585796/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20220128153009.2467560-27-peter.maydell@linaro.org/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20220128153009.2467560-27-peter.maydell@linaro.org>","list_archive_url":null,"date":"2022-01-28T15:30:03","name":"[PULL,26/32] hw/intc/arm_gicv3_its: Provide read accessor for translation_ops","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"c0b12853f0c8c0cfd6af80f5fb09f86326e1a37c","submitter":{"id":5111,"url":"http://patchwork.ozlabs.org/api/people/5111/?format=json","name":"Peter Maydell","email":"peter.maydell@linaro.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20220128153009.2467560-27-peter.maydell@linaro.org/mbox/","series":[{"id":283405,"url":"http://patchwork.ozlabs.org/api/series/283405/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=283405","date":"2022-01-28T15:29:53","name":"[PULL,01/32] Update copyright dates to 2022","version":1,"mbox":"http://patchwork.ozlabs.org/series/283405/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/1585796/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/1585796/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["bilbo.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=ETbcbFbD;\n\tdkim-atps=neutral","ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=)"],"Received":["from lists.gnu.org (lists.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby bilbo.ozlabs.org (Postfix) with ESMTPS id 4Jljk14S9Pz9t3b\n\tfor ; Sat, 29 Jan 2022 03:35:20 +1100 (AEDT)","from localhost ([::1]:34404 helo=lists1p.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from )\n\tid 1nDUDU-0004sc-UA\n\tfor incoming@patchwork.ozlabs.org; Fri, 28 Jan 2022 11:35:16 -0500","from eggs.gnu.org ([209.51.188.92]:58036)\n by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from )\n id 1nDTDM-0002Fn-Op\n for qemu-devel@nongnu.org; Fri, 28 Jan 2022 10:31:06 -0500","from [2a00:1450:4864:20::42e] (port=45766\n helo=mail-wr1-x42e.google.com)\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from )\n id 1nDTDK-0006Qh-4C\n for qemu-devel@nongnu.org; Fri, 28 Jan 2022 10:31:04 -0500","by mail-wr1-x42e.google.com with SMTP id m14so11326515wrg.12\n for ; Fri, 28 Jan 2022 07:30:39 -0800 (PST)","from orth.archaic.org.uk (orth.archaic.org.uk. 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However, if you don't\nprovide a read function and the guest tries reading from this memory\nregion, QEMU will crash because\nmemory_region_read_with_attrs_accessor() calls a NULL pointer.\n\nAdd a read function which always returns 0, to cover both bogus\nattempts to read GITS_TRANSLATER and also reads from the rest of the\nregion, which is documented to be reserved, RES0.\n\nSigned-off-by: Peter Maydell \nReviewed-by: Philippe Mathieu-Daudé \nReviewed-by: Richard Henderson \nMessage-id: 20220122182444.724087-11-peter.maydell@linaro.org\n---\n hw/intc/arm_gicv3_its.c | 13 +++++++++++++\n 1 file changed, 13 insertions(+)","diff":"diff --git a/hw/intc/arm_gicv3_its.c b/hw/intc/arm_gicv3_its.c\nindex d9ff7b88492..b17f2631269 100644\n--- a/hw/intc/arm_gicv3_its.c\n+++ b/hw/intc/arm_gicv3_its.c\n@@ -813,6 +813,18 @@ static void extract_cmdq_params(GICv3ITSState *s)\n }\n }\n \n+static MemTxResult gicv3_its_translation_read(void *opaque, hwaddr offset,\n+ uint64_t *data, unsigned size,\n+ MemTxAttrs attrs)\n+{\n+ /*\n+ * GITS_TRANSLATER is write-only, and all other addresses\n+ * in the interrupt translation space frame are RES0.\n+ */\n+ *data = 0;\n+ return MEMTX_OK;\n+}\n+\n static MemTxResult gicv3_its_translation_write(void *opaque, hwaddr offset,\n uint64_t data, unsigned size,\n MemTxAttrs attrs)\n@@ -1168,6 +1180,7 @@ static const MemoryRegionOps gicv3_its_control_ops = {\n };\n \n static const MemoryRegionOps gicv3_its_translation_ops = {\n+ .read_with_attrs = gicv3_its_translation_read,\n .write_with_attrs = gicv3_its_translation_write,\n .valid.min_access_size = 2,\n .valid.max_access_size = 4,\n","prefixes":["PULL","26/32"]}