{"id":1585775,"url":"http://patchwork.ozlabs.org/api/patches/1585775/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20220128153009.2467560-8-peter.maydell@linaro.org/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20220128153009.2467560-8-peter.maydell@linaro.org>","list_archive_url":null,"date":"2022-01-28T15:29:44","name":"[PULL,07/32] hw/arm/xlnx-versal: Connect Versal's PMC SLCR","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"2f990628afd31f88475d41330d47b761103418c5","submitter":{"id":5111,"url":"http://patchwork.ozlabs.org/api/people/5111/?format=json","name":"Peter Maydell","email":"peter.maydell@linaro.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20220128153009.2467560-8-peter.maydell@linaro.org/mbox/","series":[{"id":283405,"url":"http://patchwork.ozlabs.org/api/series/283405/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=283405","date":"2022-01-28T15:29:53","name":"[PULL,01/32] Update copyright dates to 2022","version":1,"mbox":"http://patchwork.ozlabs.org/series/283405/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/1585775/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/1585775/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["bilbo.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=eK2jYYOa;\n\tdkim-atps=neutral","ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=)"],"Received":["from lists.gnu.org (lists.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby bilbo.ozlabs.org (Postfix) with ESMTPS id 4JljBx6sz3z9t3b\n\tfor ; Sat, 29 Jan 2022 03:11:53 +1100 (AEDT)","from localhost ([::1]:56052 helo=lists1p.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from )\n\tid 1nDTqp-0005WL-OL\n\tfor incoming@patchwork.ozlabs.org; Fri, 28 Jan 2022 11:11:51 -0500","from eggs.gnu.org ([209.51.188.92]:57638)\n by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from )\n id 1nDTD5-0002AZ-NU\n for qemu-devel@nongnu.org; Fri, 28 Jan 2022 10:30:52 -0500","from [2a00:1450:4864:20::32b] (port=51037\n helo=mail-wm1-x32b.google.com)\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from )\n id 1nDTCy-0006OK-9J\n for qemu-devel@nongnu.org; Fri, 28 Jan 2022 10:30:44 -0500","by mail-wm1-x32b.google.com with SMTP id m26so2236216wms.0\n for ; Fri, 28 Jan 2022 07:30:24 -0800 (PST)","from orth.archaic.org.uk (orth.archaic.org.uk. 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+0000","Message-Id":"<20220128153009.2467560-8-peter.maydell@linaro.org>","X-Mailer":"git-send-email 2.25.1","In-Reply-To":"<20220128153009.2467560-1-peter.maydell@linaro.org>","References":"<20220128153009.2467560-1-peter.maydell@linaro.org>","MIME-Version":"1.0","Content-Transfer-Encoding":"8bit","X-Host-Lookup-Failed":"Reverse DNS lookup failed for 2a00:1450:4864:20::32b\n (failed)","Received-SPF":"pass client-ip=2a00:1450:4864:20::32b;\n envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32b.google.com","X-Spam_score_int":"-12","X-Spam_score":"-1.3","X-Spam_bar":"-","X-Spam_report":"(-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n PDS_HP_HELO_NORDNS=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793,\n SPF_HELO_NONE=0.001, SPF_PASS=-0.001,\n T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"\"Qemu-devel\"\n "},"content":"From: Francisco Iglesias \n\nConnect Versal's PMC SLCR (system-level control registers) model.\n\nSigned-off-by: Francisco Iglesias \nReviewed-by: Luc Michel \nMessage-id: 20220121161141.14389-4-francisco.iglesias@xilinx.com\nSigned-off-by: Peter Maydell \n---\n include/hw/arm/xlnx-versal.h | 5 +++\n hw/arm/xlnx-versal.c | 71 +++++++++++++++++++++++++++++++++++-\n 2 files changed, 75 insertions(+), 1 deletion(-)","diff":"diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx-versal.h\nindex 62fb6f0a688..811df73350b 100644\n--- a/include/hw/arm/xlnx-versal.h\n+++ b/include/hw/arm/xlnx-versal.h\n@@ -26,6 +26,7 @@\n #include \"hw/misc/xlnx-versal-xramc.h\"\n #include \"hw/nvram/xlnx-bbram.h\"\n #include \"hw/nvram/xlnx-versal-efuse.h\"\n+#include \"hw/misc/xlnx-versal-pmc-iou-slcr.h\"\n \n #define TYPE_XLNX_VERSAL \"xlnx-versal\"\n OBJECT_DECLARE_SIMPLE_TYPE(Versal, XLNX_VERSAL)\n@@ -78,6 +79,7 @@ struct Versal {\n struct {\n struct {\n SDHCIState sd[XLNX_VERSAL_NR_SDS];\n+ XlnxVersalPmcIouSlcr slcr;\n } iou;\n \n XlnxZynqMPRTC rtc;\n@@ -179,6 +181,9 @@ struct Versal {\n #define MM_FPD_FPD_APU 0xfd5c0000\n #define MM_FPD_FPD_APU_SIZE 0x100\n \n+#define MM_PMC_PMC_IOU_SLCR 0xf1060000\n+#define MM_PMC_PMC_IOU_SLCR_SIZE 0x10000\n+\n #define MM_PMC_SD0 0xf1040000U\n #define MM_PMC_SD0_SIZE 0x10000\n #define MM_PMC_BBRAM_CTRL 0xf11f0000\ndiff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c\nindex fefd00b57c5..c8c0c102c74 100644\n--- a/hw/arm/xlnx-versal.c\n+++ b/hw/arm/xlnx-versal.c\n@@ -21,11 +21,13 @@\n #include \"kvm_arm.h\"\n #include \"hw/misc/unimp.h\"\n #include \"hw/arm/xlnx-versal.h\"\n+#include \"qemu/log.h\"\n+#include \"hw/sysbus.h\"\n \n #define XLNX_VERSAL_ACPU_TYPE ARM_CPU_TYPE_NAME(\"cortex-a72\")\n #define GEM_REVISION 0x40070106\n \n-#define VERSAL_NUM_PMC_APB_IRQS 2\n+#define VERSAL_NUM_PMC_APB_IRQS 3\n \n static void versal_create_apu_cpus(Versal *s)\n {\n@@ -271,6 +273,7 @@ static void versal_create_pmc_apb_irq_orgate(Versal *s, qemu_irq *pic)\n * models:\n * - RTC\n * - BBRAM\n+ * - PMC SLCR\n */\n object_initialize_child(OBJECT(s), \"pmc-apb-irq-orgate\",\n &s->pmc.apb_irq_orgate, TYPE_OR_IRQ);\n@@ -392,6 +395,23 @@ static void versal_create_efuse(Versal *s, qemu_irq *pic)\n sysbus_connect_irq(SYS_BUS_DEVICE(ctrl), 0, pic[VERSAL_EFUSE_IRQ]);\n }\n \n+static void versal_create_pmc_iou_slcr(Versal *s, qemu_irq *pic)\n+{\n+ SysBusDevice *sbd;\n+\n+ object_initialize_child(OBJECT(s), \"versal-pmc-iou-slcr\", &s->pmc.iou.slcr,\n+ TYPE_XILINX_VERSAL_PMC_IOU_SLCR);\n+\n+ sbd = SYS_BUS_DEVICE(&s->pmc.iou.slcr);\n+ sysbus_realize(sbd, &error_fatal);\n+\n+ memory_region_add_subregion(&s->mr_ps, MM_PMC_PMC_IOU_SLCR,\n+ sysbus_mmio_get_region(sbd, 0));\n+\n+ sysbus_connect_irq(sbd, 0,\n+ qdev_get_gpio_in(DEVICE(&s->pmc.apb_irq_orgate), 2));\n+}\n+\n /* This takes the board allocated linear DDR memory and creates aliases\n * for each split DDR range/aperture on the Versal address map.\n */\n@@ -448,8 +468,31 @@ static void versal_unimp_area(Versal *s, const char *name,\n memory_region_add_subregion(mr, base, mr_dev);\n }\n \n+static void versal_unimp_sd_emmc_sel(void *opaque, int n, int level)\n+{\n+ qemu_log_mask(LOG_UNIMP,\n+ \"Selecting between enabling SD mode or eMMC mode on \"\n+ \"controller %d is not yet implemented\\n\", n);\n+}\n+\n+static void versal_unimp_qspi_ospi_mux_sel(void *opaque, int n, int level)\n+{\n+ qemu_log_mask(LOG_UNIMP,\n+ \"Selecting between enabling the QSPI or OSPI linear address \"\n+ \"region is not yet implemented\\n\");\n+}\n+\n+static void versal_unimp_irq_parity_imr(void *opaque, int n, int level)\n+{\n+ qemu_log_mask(LOG_UNIMP,\n+ \"PMC SLCR parity interrupt behaviour \"\n+ \"is not yet implemented\\n\");\n+}\n+\n static void versal_unimp(Versal *s)\n {\n+ qemu_irq gpio_in;\n+\n versal_unimp_area(s, \"psm\", &s->mr_ps,\n MM_PSM_START, MM_PSM_END - MM_PSM_START);\n versal_unimp_area(s, \"crl\", &s->mr_ps,\n@@ -464,6 +507,31 @@ static void versal_unimp(Versal *s)\n MM_IOU_SCNTR, MM_IOU_SCNTR_SIZE);\n versal_unimp_area(s, \"iou-scntr-seucre\", &s->mr_ps,\n MM_IOU_SCNTRS, MM_IOU_SCNTRS_SIZE);\n+\n+ qdev_init_gpio_in_named(DEVICE(s), versal_unimp_sd_emmc_sel,\n+ \"sd-emmc-sel-dummy\", 2);\n+ qdev_init_gpio_in_named(DEVICE(s), versal_unimp_qspi_ospi_mux_sel,\n+ \"qspi-ospi-mux-sel-dummy\", 1);\n+ qdev_init_gpio_in_named(DEVICE(s), versal_unimp_irq_parity_imr,\n+ \"irq-parity-imr-dummy\", 1);\n+\n+ gpio_in = qdev_get_gpio_in_named(DEVICE(s), \"sd-emmc-sel-dummy\", 0);\n+ qdev_connect_gpio_out_named(DEVICE(&s->pmc.iou.slcr), \"sd-emmc-sel\", 0,\n+ gpio_in);\n+\n+ gpio_in = qdev_get_gpio_in_named(DEVICE(s), \"sd-emmc-sel-dummy\", 1);\n+ qdev_connect_gpio_out_named(DEVICE(&s->pmc.iou.slcr), \"sd-emmc-sel\", 1,\n+ gpio_in);\n+\n+ gpio_in = qdev_get_gpio_in_named(DEVICE(s), \"qspi-ospi-mux-sel-dummy\", 0);\n+ qdev_connect_gpio_out_named(DEVICE(&s->pmc.iou.slcr),\n+ \"qspi-ospi-mux-sel\", 0,\n+ gpio_in);\n+\n+ gpio_in = qdev_get_gpio_in_named(DEVICE(s), \"irq-parity-imr-dummy\", 0);\n+ qdev_connect_gpio_out_named(DEVICE(&s->pmc.iou.slcr),\n+ SYSBUS_DEVICE_GPIO_IRQ, 0,\n+ gpio_in);\n }\n \n static void versal_realize(DeviceState *dev, Error **errp)\n@@ -483,6 +551,7 @@ static void versal_realize(DeviceState *dev, Error **errp)\n versal_create_xrams(s, pic);\n versal_create_bbram(s, pic);\n versal_create_efuse(s, pic);\n+ versal_create_pmc_iou_slcr(s, pic);\n versal_map_ddr(s);\n versal_unimp(s);\n \n","prefixes":["PULL","07/32"]}