{"id":1585746,"url":"http://patchwork.ozlabs.org/api/patches/1585746/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20220128153009.2467560-30-peter.maydell@linaro.org/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20220128153009.2467560-30-peter.maydell@linaro.org>","list_archive_url":null,"date":"2022-01-28T15:30:06","name":"[PULL,29/32] hw/intc/arm_gicv3_its: Implement MOVALL","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"3b163174f519b68fd73a745e921845b9c98e8720","submitter":{"id":5111,"url":"http://patchwork.ozlabs.org/api/people/5111/?format=json","name":"Peter Maydell","email":"peter.maydell@linaro.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20220128153009.2467560-30-peter.maydell@linaro.org/mbox/","series":[{"id":283405,"url":"http://patchwork.ozlabs.org/api/series/283405/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=283405","date":"2022-01-28T15:29:53","name":"[PULL,01/32] Update copyright dates to 2022","version":1,"mbox":"http://patchwork.ozlabs.org/series/283405/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/1585746/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/1585746/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["bilbo.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=zl+xF80p;\n\tdkim-atps=neutral","ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=)"],"Received":["from lists.gnu.org (lists.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby bilbo.ozlabs.org (Postfix) with ESMTPS id 4Jlhyc4zJjz9t3b\n\tfor ; Sat, 29 Jan 2022 03:01:11 +1100 (AEDT)","from localhost ([::1]:44150 helo=lists1p.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from )\n\tid 1nDTgR-0005I0-C6\n\tfor incoming@patchwork.ozlabs.org; Fri, 28 Jan 2022 11:01:07 -0500","from eggs.gnu.org ([209.51.188.92]:57922)\n by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from )\n id 1nDTDK-0002Dm-4I\n for qemu-devel@nongnu.org; Fri, 28 Jan 2022 10:31:03 -0500","from [2a00:1450:4864:20::32d] (port=37424\n helo=mail-wm1-x32d.google.com)\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from )\n id 1nDTDD-0006R4-Tq\n for qemu-devel@nongnu.org; Fri, 28 Jan 2022 10:30:58 -0500","by mail-wm1-x32d.google.com with SMTP id\n l12-20020a7bc34c000000b003467c58cbdfso8456191wmj.2\n for ; Fri, 28 Jan 2022 07:30:41 -0800 (PST)","from orth.archaic.org.uk (orth.archaic.org.uk. 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(It is\nnot used by Linux guests.)\n\nSigned-off-by: Peter Maydell \nReviewed-by: Richard Henderson \nMessage-id: 20220122182444.724087-14-peter.maydell@linaro.org\n---\n hw/intc/gicv3_internal.h | 16 +++++++++++\n hw/intc/arm_gicv3_its.c | 55 ++++++++++++++++++++++++++++++++++++++\n hw/intc/arm_gicv3_redist.c | 54 +++++++++++++++++++++++++++++++++++++\n 3 files changed, 125 insertions(+)","diff":"diff --git a/hw/intc/gicv3_internal.h b/hw/intc/gicv3_internal.h\nindex a316f6c58a5..da45975d92b 100644\n--- a/hw/intc/gicv3_internal.h\n+++ b/hw/intc/gicv3_internal.h\n@@ -324,6 +324,7 @@ FIELD(GITS_TYPER, CIL, 36, 1)\n #define GITS_CMD_MAPI 0x0B\n #define GITS_CMD_INV 0x0C\n #define GITS_CMD_INVALL 0x0D\n+#define GITS_CMD_MOVALL 0x0E\n #define GITS_CMD_DISCARD 0x0F\n \n /* MAPC command fields */\n@@ -355,6 +356,10 @@ FIELD(MAPC, RDBASE, 16, 32)\n #define L2_TABLE_VALID_MASK CMD_FIELD_VALID_MASK\n #define TABLE_ENTRY_VALID_MASK (1ULL << 0)\n \n+/* MOVALL command fields */\n+FIELD(MOVALL_2, RDBASE1, 16, 36)\n+FIELD(MOVALL_3, RDBASE2, 16, 36)\n+\n /*\n * 12 bytes Interrupt translation Table Entry size\n * as per Table 5.3 in GICv3 spec\n@@ -497,6 +502,17 @@ void gicv3_redist_update_lpi(GICv3CPUState *cs);\n * an incoming migration has loaded new state.\n */\n void gicv3_redist_update_lpi_only(GICv3CPUState *cs);\n+/**\n+ * gicv3_redist_movall_lpis:\n+ * @src: source redistributor\n+ * @dest: destination redistributor\n+ *\n+ * Scan the LPI pending table for @src, and for each pending LPI there\n+ * mark it as not-pending for @src and pending for @dest, as required\n+ * by the ITS MOVALL command.\n+ */\n+void gicv3_redist_movall_lpis(GICv3CPUState *src, GICv3CPUState *dest);\n+\n void gicv3_redist_send_sgi(GICv3CPUState *cs, int grp, int irq, bool ns);\n void gicv3_init_cpuif(GICv3State *s);\n \ndiff --git a/hw/intc/arm_gicv3_its.c b/hw/intc/arm_gicv3_its.c\nindex 3f2ead45369..ebc0403b3c7 100644\n--- a/hw/intc/arm_gicv3_its.c\n+++ b/hw/intc/arm_gicv3_its.c\n@@ -582,6 +582,58 @@ static ItsCmdResult process_mapd(GICv3ITSState *s, uint64_t value,\n return update_dte(s, devid, valid, size, itt_addr) ? CMD_CONTINUE : CMD_STALL;\n }\n \n+static ItsCmdResult process_movall(GICv3ITSState *s, uint64_t value,\n+ uint32_t offset)\n+{\n+ AddressSpace *as = &s->gicv3->dma_as;\n+ MemTxResult res = MEMTX_OK;\n+ uint64_t rd1, rd2;\n+\n+ /* No fields in dwords 0 or 1 */\n+ offset += NUM_BYTES_IN_DW;\n+ offset += NUM_BYTES_IN_DW;\n+ value = address_space_ldq_le(as, s->cq.base_addr + offset,\n+ MEMTXATTRS_UNSPECIFIED, &res);\n+ if (res != MEMTX_OK) {\n+ return CMD_STALL;\n+ }\n+\n+ rd1 = FIELD_EX64(value, MOVALL_2, RDBASE1);\n+ if (rd1 >= s->gicv3->num_cpu) {\n+ qemu_log_mask(LOG_GUEST_ERROR,\n+ \"%s: RDBASE1 %\" PRId64\n+ \" out of range (must be less than %d)\\n\",\n+ __func__, rd1, s->gicv3->num_cpu);\n+ return CMD_CONTINUE;\n+ }\n+\n+ offset += NUM_BYTES_IN_DW;\n+ value = address_space_ldq_le(as, s->cq.base_addr + offset,\n+ MEMTXATTRS_UNSPECIFIED, &res);\n+ if (res != MEMTX_OK) {\n+ return CMD_STALL;\n+ }\n+\n+ rd2 = FIELD_EX64(value, MOVALL_3, RDBASE2);\n+ if (rd2 >= s->gicv3->num_cpu) {\n+ qemu_log_mask(LOG_GUEST_ERROR,\n+ \"%s: RDBASE2 %\" PRId64\n+ \" out of range (must be less than %d)\\n\",\n+ __func__, rd2, s->gicv3->num_cpu);\n+ return CMD_CONTINUE;\n+ }\n+\n+ if (rd1 == rd2) {\n+ /* Move to same target must succeed as a no-op */\n+ return CMD_CONTINUE;\n+ }\n+\n+ /* Move all pending LPIs from redistributor 1 to redistributor 2 */\n+ gicv3_redist_movall_lpis(&s->gicv3->cpu[rd1], &s->gicv3->cpu[rd2]);\n+\n+ return CMD_CONTINUE;\n+}\n+\n /*\n * Current implementation blocks until all\n * commands are processed\n@@ -679,6 +731,9 @@ static void process_cmdq(GICv3ITSState *s)\n gicv3_redist_update_lpi(&s->gicv3->cpu[i]);\n }\n break;\n+ case GITS_CMD_MOVALL:\n+ result = process_movall(s, data, cq_offset);\n+ break;\n default:\n break;\n }\ndiff --git a/hw/intc/arm_gicv3_redist.c b/hw/intc/arm_gicv3_redist.c\nindex d81d8e5f076..d1645ba22c6 100644\n--- a/hw/intc/arm_gicv3_redist.c\n+++ b/hw/intc/arm_gicv3_redist.c\n@@ -681,6 +681,60 @@ void gicv3_redist_process_lpi(GICv3CPUState *cs, int irq, int level)\n gicv3_redist_lpi_pending(cs, irq, level);\n }\n \n+void gicv3_redist_movall_lpis(GICv3CPUState *src, GICv3CPUState *dest)\n+{\n+ /*\n+ * We must move all pending LPIs from the source redistributor\n+ * to the destination. That is, for every pending LPI X on\n+ * src, we must set it not-pending on src and pending on dest.\n+ * LPIs that are already pending on dest are not cleared.\n+ *\n+ * If LPIs are disabled on dest this is CONSTRAINED UNPREDICTABLE:\n+ * we choose to NOP. If LPIs are disabled on source there's nothing\n+ * to be transferred anyway.\n+ */\n+ AddressSpace *as = &src->gic->dma_as;\n+ uint64_t idbits;\n+ uint32_t pendt_size;\n+ uint64_t src_baddr, dest_baddr;\n+ int i;\n+\n+ if (!(src->gicr_ctlr & GICR_CTLR_ENABLE_LPIS) ||\n+ !(dest->gicr_ctlr & GICR_CTLR_ENABLE_LPIS)) {\n+ return;\n+ }\n+\n+ idbits = MIN(FIELD_EX64(src->gicr_propbaser, GICR_PROPBASER, IDBITS),\n+ GICD_TYPER_IDBITS);\n+ idbits = MIN(FIELD_EX64(dest->gicr_propbaser, GICR_PROPBASER, IDBITS),\n+ idbits);\n+\n+ pendt_size = 1ULL << (idbits + 1);\n+ src_baddr = src->gicr_pendbaser & R_GICR_PENDBASER_PHYADDR_MASK;\n+ dest_baddr = dest->gicr_pendbaser & R_GICR_PENDBASER_PHYADDR_MASK;\n+\n+ for (i = GICV3_LPI_INTID_START / 8; i < pendt_size / 8; i++) {\n+ uint8_t src_pend, dest_pend;\n+\n+ address_space_read(as, src_baddr + i, MEMTXATTRS_UNSPECIFIED,\n+ &src_pend, sizeof(src_pend));\n+ if (!src_pend) {\n+ continue;\n+ }\n+ address_space_read(as, dest_baddr + i, MEMTXATTRS_UNSPECIFIED,\n+ &dest_pend, sizeof(dest_pend));\n+ dest_pend |= src_pend;\n+ src_pend = 0;\n+ address_space_write(as, src_baddr + i, MEMTXATTRS_UNSPECIFIED,\n+ &src_pend, sizeof(src_pend));\n+ address_space_write(as, dest_baddr + i, MEMTXATTRS_UNSPECIFIED,\n+ &dest_pend, sizeof(dest_pend));\n+ }\n+\n+ gicv3_redist_update_lpi(src);\n+ gicv3_redist_update_lpi(dest);\n+}\n+\n void gicv3_redist_set_irq(GICv3CPUState *cs, int irq, int level)\n {\n /* Update redistributor state for a change in an external PPI input line */\n","prefixes":["PULL","29/32"]}