{"id":1447394,"url":"http://patchwork.ozlabs.org/api/patches/1447394/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20210304144651.310037-18-alistair.francis@wdc.com/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20210304144651.310037-18-alistair.francis@wdc.com>","list_archive_url":null,"date":"2021-03-04T14:46:49","name":"[PULL,v2,17/19] hw/riscv: virt: Drop the 'link_up' parameter of gpex_pcie_init()","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"c95d4df3e7403ae4f3d2d82ce2017c6ccec37dbc","submitter":{"id":74007,"url":"http://patchwork.ozlabs.org/api/people/74007/?format=json","name":"Alistair Francis","email":"alistair.francis@wdc.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20210304144651.310037-18-alistair.francis@wdc.com/mbox/","series":[{"id":232161,"url":"http://patchwork.ozlabs.org/api/series/232161/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=232161","date":"2021-03-04T14:46:33","name":"[PULL,v2,01/19] target/riscv: Declare csr_ops[] with a known size","version":2,"mbox":"http://patchwork.ozlabs.org/series/232161/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/1447394/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/1447394/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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d=\"scan'208\";a=\"271984433\"","WDCIronportException":"Internal","From":"Alistair Francis ","To":"peter.maydell@linaro.org","Subject":"[PULL v2 17/19] hw/riscv: virt: Drop the 'link_up' parameter of\n gpex_pcie_init()","Date":"Thu, 4 Mar 2021 09:46:49 -0500","Message-Id":"<20210304144651.310037-18-alistair.francis@wdc.com>","X-Mailer":"git-send-email 2.30.1","In-Reply-To":"<20210304144651.310037-1-alistair.francis@wdc.com>","References":"<20210304144651.310037-1-alistair.francis@wdc.com>","MIME-Version":"1.0","Content-Transfer-Encoding":"8bit","Received-SPF":"pass client-ip=68.232.141.245;\n envelope-from=prvs=690dc056c=alistair.francis@wdc.com;\n helo=esa1.hgst.iphmx.com","X-Spam_score_int":"-27","X-Spam_score":"-2.8","X-Spam_bar":"--","X-Spam_report":"(-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_PASS=-0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.23","Precedence":"list","List-Id":"","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Cc":"alistair23@gmail.com, Bin Meng ,\n Alistair Francis , qemu-devel@nongnu.org","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"\"Qemu-devel\"\n "},"content":"From: Bin Meng \n\n`link_up` is never used in gpex_pcie_init(). Drop it.\n\nSigned-off-by: Bin Meng \nReviewed-by: Alistair Francis \nMessage-id: 20210220144807.819-3-bmeng.cn@gmail.com\nSigned-off-by: Alistair Francis \n---\n hw/riscv/virt.c | 14 +++++++-------\n 1 file changed, 7 insertions(+), 7 deletions(-)","diff":"diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c\nindex cfd52bc59b..1d05bb3ef9 100644\n--- a/hw/riscv/virt.c\n+++ b/hw/riscv/virt.c\n@@ -449,7 +449,7 @@ static inline DeviceState *gpex_pcie_init(MemoryRegion *sys_mem,\n hwaddr ecam_base, hwaddr ecam_size,\n hwaddr mmio_base, hwaddr mmio_size,\n hwaddr pio_base,\n- DeviceState *plic, bool link_up)\n+ DeviceState *plic)\n {\n DeviceState *dev;\n MemoryRegion *ecam_alias, *ecam_reg;\n@@ -669,12 +669,12 @@ static void virt_machine_init(MachineState *machine)\n }\n \n gpex_pcie_init(system_memory,\n- memmap[VIRT_PCIE_ECAM].base,\n- memmap[VIRT_PCIE_ECAM].size,\n- memmap[VIRT_PCIE_MMIO].base,\n- memmap[VIRT_PCIE_MMIO].size,\n- memmap[VIRT_PCIE_PIO].base,\n- DEVICE(pcie_plic), true);\n+ memmap[VIRT_PCIE_ECAM].base,\n+ memmap[VIRT_PCIE_ECAM].size,\n+ memmap[VIRT_PCIE_MMIO].base,\n+ memmap[VIRT_PCIE_MMIO].size,\n+ memmap[VIRT_PCIE_PIO].base,\n+ DEVICE(pcie_plic));\n \n serial_mm_init(system_memory, memmap[VIRT_UART0].base,\n 0, qdev_get_gpio_in(DEVICE(mmio_plic), UART0_IRQ), 399193,\n","prefixes":["PULL","v2","17/19"]}