{"id":1447393,"url":"http://patchwork.ozlabs.org/api/patches/1447393/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20210304144651.310037-9-alistair.francis@wdc.com/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20210304144651.310037-9-alistair.francis@wdc.com>","list_archive_url":null,"date":"2021-03-04T14:46:40","name":"[PULL,v2,08/19] hw/riscv: sifive_u: Add QSPI0 controller and connect a flash","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"efa71cbd88012bb227b55d079dbaa37b87500d52","submitter":{"id":74007,"url":"http://patchwork.ozlabs.org/api/people/74007/?format=json","name":"Alistair Francis","email":"alistair.francis@wdc.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20210304144651.310037-9-alistair.francis@wdc.com/mbox/","series":[{"id":232161,"url":"http://patchwork.ozlabs.org/api/series/232161/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=232161","date":"2021-03-04T14:46:33","name":"[PULL,v2,01/19] target/riscv: Declare csr_ops[] with a known size","version":2,"mbox":"http://patchwork.ozlabs.org/series/232161/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/1447393/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/1447393/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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d=\"scan'208\";a=\"271984410\"","WDCIronportException":"Internal","From":"Alistair Francis ","To":"peter.maydell@linaro.org","Subject":"[PULL v2 08/19] hw/riscv: sifive_u: Add QSPI0 controller and connect\n a flash","Date":"Thu, 4 Mar 2021 09:46:40 -0500","Message-Id":"<20210304144651.310037-9-alistair.francis@wdc.com>","X-Mailer":"git-send-email 2.30.1","In-Reply-To":"<20210304144651.310037-1-alistair.francis@wdc.com>","References":"<20210304144651.310037-1-alistair.francis@wdc.com>","MIME-Version":"1.0","Content-Transfer-Encoding":"8bit","Received-SPF":"pass client-ip=68.232.141.245;\n envelope-from=prvs=690dc056c=alistair.francis@wdc.com;\n helo=esa1.hgst.iphmx.com","X-Spam_score_int":"-27","X-Spam_score":"-2.8","X-Spam_bar":"--","X-Spam_report":"(-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_PASS=-0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.23","Precedence":"list","List-Id":"","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Cc":"alistair23@gmail.com, Bin Meng ,\n Alistair Francis , qemu-devel@nongnu.org","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"\"Qemu-devel\"\n "},"content":"From: Bin Meng \n\nThis adds the QSPI0 controller to the SoC, and connects an ISSI\n25WP256 flash to it. The generation of corresponding device tree\nsource fragment is also added.\n\nSince the direct memory-mapped mode is not supported by the SiFive\nSPI model, the property does not populate the second group\nwhich represents the memory mapped address of the SPI flash.\n\nWith this commit, upstream U-Boot for the SiFive HiFive Unleashed\nboard can boot on QEMU 'sifive_u' out of the box. This allows users\nto develop and test the recommended RISC-V boot flow with a real\nworld use case: ZSBL (in QEMU) loads U-Boot SPL from SPI flash to\nL2LIM, then U-Boot SPL loads the payload from SPI flash that is\ncombined with OpenSBI fw_dynamic firmware and U-Boot proper.\n\nSpecify machine property `msel` to 6 to allow booting from the SPI\nflash. U-Boot spl is directly loaded via `-bios`, and subsequent\npayload is stored in the SPI flash image. Example command line:\n\n$ qemu-system-riscv64 -nographic -M sifive_u,msel=6 -smp 5 -m 8G \\\n -bios u-boot-spl.bin -drive file=spi-nor.img,if=mtd\n\nSigned-off-by: Bin Meng \nReviewed-by: Alistair Francis \nMessage-id: 20210126060007.12904-5-bmeng.cn@gmail.com\nSigned-off-by: Alistair Francis \n---\n include/hw/riscv/sifive_u.h | 4 +++\n hw/riscv/sifive_u.c | 52 +++++++++++++++++++++++++++++++++++++\n hw/riscv/Kconfig | 2 ++\n 3 files changed, 58 insertions(+)","diff":"diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h\nindex a9f7b4a084..8824b7c031 100644\n--- a/include/hw/riscv/sifive_u.h\n+++ b/include/hw/riscv/sifive_u.h\n@@ -26,6 +26,7 @@\n #include \"hw/gpio/sifive_gpio.h\"\n #include \"hw/misc/sifive_u_otp.h\"\n #include \"hw/misc/sifive_u_prci.h\"\n+#include \"hw/ssi/sifive_spi.h\"\n \n #define TYPE_RISCV_U_SOC \"riscv.sifive.u.soc\"\n #define RISCV_U_SOC(obj) \\\n@@ -45,6 +46,7 @@ typedef struct SiFiveUSoCState {\n SIFIVEGPIOState gpio;\n SiFiveUOTPState otp;\n SiFivePDMAState dma;\n+ SiFiveSPIState spi0;\n CadenceGEMState gem;\n \n uint32_t serial;\n@@ -82,6 +84,7 @@ enum {\n SIFIVE_U_DEV_UART0,\n SIFIVE_U_DEV_UART1,\n SIFIVE_U_DEV_GPIO,\n+ SIFIVE_U_DEV_QSPI0,\n SIFIVE_U_DEV_OTP,\n SIFIVE_U_DEV_DMC,\n SIFIVE_U_DEV_FLASH0,\n@@ -120,6 +123,7 @@ enum {\n SIFIVE_U_PDMA_IRQ5 = 28,\n SIFIVE_U_PDMA_IRQ6 = 29,\n SIFIVE_U_PDMA_IRQ7 = 30,\n+ SIFIVE_U_QSPI0_IRQ = 51,\n SIFIVE_U_GEM_IRQ = 0x35\n };\n \ndiff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c\nindex 59b61cea01..43a0e983d2 100644\n--- a/hw/riscv/sifive_u.c\n+++ b/hw/riscv/sifive_u.c\n@@ -15,6 +15,7 @@\n * 5) OTP (One-Time Programmable) memory with stored serial number\n * 6) GEM (Gigabit Ethernet Controller) and management block\n * 7) DMA (Direct Memory Access Controller)\n+ * 8) SPI0 connected to an SPI flash\n *\n * This board currently generates devicetree dynamically that indicates at least\n * two harts and up to five harts.\n@@ -44,6 +45,7 @@\n #include \"hw/char/serial.h\"\n #include \"hw/cpu/cluster.h\"\n #include \"hw/misc/unimp.h\"\n+#include \"hw/ssi/ssi.h\"\n #include \"target/riscv/cpu.h\"\n #include \"hw/riscv/riscv_hart.h\"\n #include \"hw/riscv/sifive_u.h\"\n@@ -74,6 +76,7 @@ static const struct MemmapEntry {\n [SIFIVE_U_DEV_PRCI] = { 0x10000000, 0x1000 },\n [SIFIVE_U_DEV_UART0] = { 0x10010000, 0x1000 },\n [SIFIVE_U_DEV_UART1] = { 0x10011000, 0x1000 },\n+ [SIFIVE_U_DEV_QSPI0] = { 0x10040000, 0x1000 },\n [SIFIVE_U_DEV_GPIO] = { 0x10060000, 0x1000 },\n [SIFIVE_U_DEV_OTP] = { 0x10070000, 0x1000 },\n [SIFIVE_U_DEV_GEM] = { 0x10090000, 0x2000 },\n@@ -342,6 +345,32 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,\n \"sifive,fu540-c000-ccache\");\n g_free(nodename);\n \n+ nodename = g_strdup_printf(\"/soc/spi@%lx\",\n+ (long)memmap[SIFIVE_U_DEV_QSPI0].base);\n+ qemu_fdt_add_subnode(fdt, nodename);\n+ qemu_fdt_setprop_cell(fdt, nodename, \"#size-cells\", 0);\n+ qemu_fdt_setprop_cell(fdt, nodename, \"#address-cells\", 1);\n+ qemu_fdt_setprop_cells(fdt, nodename, \"clocks\",\n+ prci_phandle, PRCI_CLK_TLCLK);\n+ qemu_fdt_setprop_cell(fdt, nodename, \"interrupts\", SIFIVE_U_QSPI0_IRQ);\n+ qemu_fdt_setprop_cell(fdt, nodename, \"interrupt-parent\", plic_phandle);\n+ qemu_fdt_setprop_cells(fdt, nodename, \"reg\",\n+ 0x0, memmap[SIFIVE_U_DEV_QSPI0].base,\n+ 0x0, memmap[SIFIVE_U_DEV_QSPI0].size);\n+ qemu_fdt_setprop_string(fdt, nodename, \"compatible\", \"sifive,spi0\");\n+ g_free(nodename);\n+\n+ nodename = g_strdup_printf(\"/soc/spi@%lx/flash@0\",\n+ (long)memmap[SIFIVE_U_DEV_QSPI0].base);\n+ qemu_fdt_add_subnode(fdt, nodename);\n+ qemu_fdt_setprop_cell(fdt, nodename, \"spi-rx-bus-width\", 4);\n+ qemu_fdt_setprop_cell(fdt, nodename, \"spi-tx-bus-width\", 4);\n+ qemu_fdt_setprop(fdt, nodename, \"m25p,fast-read\", NULL, 0);\n+ qemu_fdt_setprop_cell(fdt, nodename, \"spi-max-frequency\", 50000000);\n+ qemu_fdt_setprop_cell(fdt, nodename, \"reg\", 0);\n+ qemu_fdt_setprop_string(fdt, nodename, \"compatible\", \"jedec,spi-nor\");\n+ g_free(nodename);\n+\n phy_phandle = phandle++;\n nodename = g_strdup_printf(\"/soc/ethernet@%lx\",\n (long)memmap[SIFIVE_U_DEV_GEM].base);\n@@ -439,6 +468,9 @@ static void sifive_u_machine_init(MachineState *machine)\n int i;\n uint32_t fdt_load_addr;\n uint64_t kernel_entry;\n+ DriveInfo *dinfo;\n+ DeviceState *flash_dev;\n+ qemu_irq flash_cs;\n \n /* Initialize SoC */\n object_initialize_child(OBJECT(machine), \"soc\", &s->soc, TYPE_RISCV_U_SOC);\n@@ -571,6 +603,19 @@ static void sifive_u_machine_init(MachineState *machine)\n riscv_rom_copy_firmware_info(machine, memmap[SIFIVE_U_DEV_MROM].base,\n memmap[SIFIVE_U_DEV_MROM].size,\n sizeof(reset_vec), kernel_entry);\n+\n+ /* Connect an SPI flash to SPI0 */\n+ flash_dev = qdev_new(\"is25wp256\");\n+ dinfo = drive_get_next(IF_MTD);\n+ if (dinfo) {\n+ qdev_prop_set_drive_err(flash_dev, \"drive\",\n+ blk_by_legacy_dinfo(dinfo),\n+ &error_fatal);\n+ }\n+ qdev_realize_and_unref(flash_dev, BUS(s->soc.spi0.spi), &error_fatal);\n+\n+ flash_cs = qdev_get_gpio_in_named(flash_dev, SSI_GPIO_CS, 0);\n+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->soc.spi0), 1, flash_cs);\n }\n \n static bool sifive_u_machine_get_start_in_flash(Object *obj, Error **errp)\n@@ -680,6 +725,7 @@ static void sifive_u_soc_instance_init(Object *obj)\n object_initialize_child(obj, \"gem\", &s->gem, TYPE_CADENCE_GEM);\n object_initialize_child(obj, \"gpio\", &s->gpio, TYPE_SIFIVE_GPIO);\n object_initialize_child(obj, \"pdma\", &s->dma, TYPE_SIFIVE_PDMA);\n+ object_initialize_child(obj, \"spi0\", &s->spi0, TYPE_SIFIVE_SPI);\n }\n \n static void sifive_u_soc_realize(DeviceState *dev, Error **errp)\n@@ -827,6 +873,12 @@ static void sifive_u_soc_realize(DeviceState *dev, Error **errp)\n \n create_unimplemented_device(\"riscv.sifive.u.l2cc\",\n memmap[SIFIVE_U_DEV_L2CC].base, memmap[SIFIVE_U_DEV_L2CC].size);\n+\n+ sysbus_realize(SYS_BUS_DEVICE(&s->spi0), errp);\n+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi0), 0,\n+ memmap[SIFIVE_U_DEV_QSPI0].base);\n+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi0), 0,\n+ qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_QSPI0_IRQ));\n }\n \n static Property sifive_u_soc_props[] = {\ndiff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig\nindex facb0cbacc..6330297b4e 100644\n--- a/hw/riscv/Kconfig\n+++ b/hw/riscv/Kconfig\n@@ -52,9 +52,11 @@ config SIFIVE_U\n select SIFIVE_GPIO\n select SIFIVE_PDMA\n select SIFIVE_PLIC\n+ select SIFIVE_SPI\n select SIFIVE_UART\n select SIFIVE_U_OTP\n select SIFIVE_U_PRCI\n+ select SSI_M25P80\n select UNIMP\n \n config SPIKE\n","prefixes":["PULL","v2","08/19"]}