{"id":1447392,"url":"http://patchwork.ozlabs.org/api/patches/1447392/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20210304144651.310037-13-alistair.francis@wdc.com/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20210304144651.310037-13-alistair.francis@wdc.com>","list_archive_url":null,"date":"2021-03-04T14:46:44","name":"[PULL,v2,12/19] docs/system: Add RISC-V documentation","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"0cc6561d40580494021aad6d8a60847d8bf75456","submitter":{"id":74007,"url":"http://patchwork.ozlabs.org/api/people/74007/?format=json","name":"Alistair Francis","email":"alistair.francis@wdc.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20210304144651.310037-13-alistair.francis@wdc.com/mbox/","series":[{"id":232161,"url":"http://patchwork.ozlabs.org/api/series/232161/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=232161","date":"2021-03-04T14:46:33","name":"[PULL,v2,01/19] target/riscv: Declare csr_ops[] with a known size","version":2,"mbox":"http://patchwork.ozlabs.org/series/232161/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/1447392/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/1447392/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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d=\"scan'208\";a=\"271984421\"","WDCIronportException":"Internal","From":"Alistair Francis ","To":"peter.maydell@linaro.org","Subject":"[PULL v2 12/19] docs/system: Add RISC-V documentation","Date":"Thu, 4 Mar 2021 09:46:44 -0500","Message-Id":"<20210304144651.310037-13-alistair.francis@wdc.com>","X-Mailer":"git-send-email 2.30.1","In-Reply-To":"<20210304144651.310037-1-alistair.francis@wdc.com>","References":"<20210304144651.310037-1-alistair.francis@wdc.com>","MIME-Version":"1.0","Content-Transfer-Encoding":"8bit","Received-SPF":"pass client-ip=68.232.141.245;\n envelope-from=prvs=690dc056c=alistair.francis@wdc.com;\n helo=esa1.hgst.iphmx.com","X-Spam_score_int":"-27","X-Spam_score":"-2.8","X-Spam_bar":"--","X-Spam_report":"(-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_PASS=-0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.23","Precedence":"list","List-Id":"","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Cc":"alistair23@gmail.com, Bin Meng ,\n Alistair Francis , qemu-devel@nongnu.org","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"\"Qemu-devel\"\n "},"content":"From: Bin Meng \n\nAdd RISC-V system emulator documentation for generic information.\n`Board-specific documentation` and `RISC-V CPU features` are only\na placeholder and will be added in the future.\n\nSigned-off-by: Bin Meng \nReviewed-by: Alistair Francis \nMessage-id: 20210126060007.12904-9-bmeng.cn@gmail.com\nSigned-off-by: Alistair Francis \n---\n docs/system/target-riscv.rst | 62 ++++++++++++++++++++++++++++++++++++\n docs/system/targets.rst | 1 +\n 2 files changed, 63 insertions(+)\n create mode 100644 docs/system/target-riscv.rst","diff":"diff --git a/docs/system/target-riscv.rst b/docs/system/target-riscv.rst\nnew file mode 100644\nindex 0000000000..9f4b7586e5\n--- /dev/null\n+++ b/docs/system/target-riscv.rst\n@@ -0,0 +1,62 @@\n+.. _RISC-V-System-emulator:\n+\n+RISC-V System emulator\n+======================\n+\n+QEMU can emulate both 32-bit and 64-bit RISC-V CPUs. Use the\n+``qemu-system-riscv64`` executable to simulate a 64-bit RISC-V machine,\n+``qemu-system-riscv32`` executable to simulate a 32-bit RISC-V machine.\n+\n+QEMU has generally good support for RISC-V guests. It has support for\n+several different machines. The reason we support so many is that\n+RISC-V hardware is much more widely varying than x86 hardware. RISC-V\n+CPUs are generally built into \"system-on-chip\" (SoC) designs created by\n+many different companies with different devices, and these SoCs are\n+then built into machines which can vary still further even if they use\n+the same SoC.\n+\n+For most boards the CPU type is fixed (matching what the hardware has),\n+so typically you don't need to specify the CPU type by hand, except for\n+special cases like the ``virt`` board.\n+\n+Choosing a board model\n+----------------------\n+\n+For QEMU's RISC-V system emulation, you must specify which board\n+model you want to use with the ``-M`` or ``--machine`` option;\n+there is no default.\n+\n+Because RISC-V systems differ so much and in fundamental ways, typically\n+operating system or firmware images intended to run on one machine\n+will not run at all on any other. This is often surprising for new\n+users who are used to the x86 world where every system looks like a\n+standard PC. (Once the kernel has booted, most user space software\n+cares much less about the detail of the hardware.)\n+\n+If you already have a system image or a kernel that works on hardware\n+and you want to boot with QEMU, check whether QEMU lists that machine\n+in its ``-machine help`` output. If it is listed, then you can probably\n+use that board model. If it is not listed, then unfortunately your image\n+will almost certainly not boot on QEMU. (You might be able to\n+extract the file system and use that with a different kernel which\n+boots on a system that QEMU does emulate.)\n+\n+If you don't care about reproducing the idiosyncrasies of a particular\n+bit of hardware, such as small amount of RAM, no PCI or other hard\n+disk, etc., and just want to run Linux, the best option is to use the\n+``virt`` board. This is a platform which doesn't correspond to any\n+real hardware and is designed for use in virtual machines. You'll\n+need to compile Linux with a suitable configuration for running on\n+the ``virt`` board. ``virt`` supports PCI, virtio, recent CPUs and\n+large amounts of RAM. It also supports 64-bit CPUs.\n+\n+Board-specific documentation\n+----------------------------\n+\n+Unfortunately many of the RISC-V boards QEMU supports are currently\n+undocumented; you can get a complete list by running\n+``qemu-system-riscv64 --machine help``, or\n+``qemu-system-riscv32 --machine help``.\n+\n+RISC-V CPU features\n+-------------------\ndiff --git a/docs/system/targets.rst b/docs/system/targets.rst\nindex 564cea9a9b..75ed1087fd 100644\n--- a/docs/system/targets.rst\n+++ b/docs/system/targets.rst\n@@ -19,6 +19,7 @@ Contents:\n target-m68k\n target-mips\n target-ppc\n+ target-riscv\n target-rx\n target-s390x\n target-sparc\n","prefixes":["PULL","v2","12/19"]}