{"id":1447387,"url":"http://patchwork.ozlabs.org/api/patches/1447387/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20210304144651.310037-6-alistair.francis@wdc.com/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20210304144651.310037-6-alistair.francis@wdc.com>","list_archive_url":null,"date":"2021-03-04T14:46:37","name":"[PULL,v2,05/19] hw/block: m25p80: Add ISSI SPI flash support","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"649031dc2a1d4b2a9472a3b55536e164f9c4181a","submitter":{"id":74007,"url":"http://patchwork.ozlabs.org/api/people/74007/?format=json","name":"Alistair Francis","email":"alistair.francis@wdc.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20210304144651.310037-6-alistair.francis@wdc.com/mbox/","series":[{"id":232161,"url":"http://patchwork.ozlabs.org/api/series/232161/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=232161","date":"2021-03-04T14:46:33","name":"[PULL,v2,01/19] target/riscv: Declare csr_ops[] with a known size","version":2,"mbox":"http://patchwork.ozlabs.org/series/232161/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/1447387/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/1447387/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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d=\"scan'208\";a=\"271984406\"","WDCIronportException":"Internal","From":"Alistair Francis ","To":"peter.maydell@linaro.org","Subject":"[PULL v2 05/19] hw/block: m25p80: Add ISSI SPI flash support","Date":"Thu, 4 Mar 2021 09:46:37 -0500","Message-Id":"<20210304144651.310037-6-alistair.francis@wdc.com>","X-Mailer":"git-send-email 2.30.1","In-Reply-To":"<20210304144651.310037-1-alistair.francis@wdc.com>","References":"<20210304144651.310037-1-alistair.francis@wdc.com>","MIME-Version":"1.0","Content-Transfer-Encoding":"8bit","Received-SPF":"pass client-ip=68.232.141.245;\n envelope-from=prvs=690dc056c=alistair.francis@wdc.com;\n helo=esa1.hgst.iphmx.com","X-Spam_score_int":"-27","X-Spam_score":"-2.8","X-Spam_bar":"--","X-Spam_report":"(-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_PASS=-0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.23","Precedence":"list","List-Id":"","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Cc":"alistair23@gmail.com, Bin Meng ,\n Alistair Francis , qemu-devel@nongnu.org","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"\"Qemu-devel\"\n "},"content":"From: Bin Meng \n\nThis adds the ISSI SPI flash support. The number of dummy cycles in\nfast read, fast read dual output and fast read quad output commands\nis currently using the default 8. Likewise, the same default value\nis used for fast read dual/quad I/O command. Per the datasheet [1],\nthe number of dummy cycles is configurable, but this is not modeled\nat present.\n\nFor flash whose size is larger than 16 MiB, the sequence of 3-byte\naddress along with EXTADD bit in the bank address register (BAR) is\nnot supported. We assume that guest software always uses op codes\nwith 4-byte address sequence. Fortunately, this is the case for both\nU-Boot and Linux spi-nor drivers.\n\nQPI (Quad Peripheral Interface) that supports 2-cycle instruction\nhas different default values for dummy cycles of fast read family\ncommands, and is unsupported at the time being.\n\n[1] http://www.issi.com/WW/pdf/25LP-WP256.pdf\n\nSigned-off-by: Bin Meng \nAcked-by: Alistair Francis \nMessage-id: 20210126060007.12904-2-bmeng.cn@gmail.com\nSigned-off-by: Alistair Francis \n---\n hw/block/m25p80.c | 44 +++++++++++++++++++++++++++++++++++++++++++-\n 1 file changed, 43 insertions(+), 1 deletion(-)","diff":"diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c\nindex 0412d3e7f4..ad4456b74e 100644\n--- a/hw/block/m25p80.c\n+++ b/hw/block/m25p80.c\n@@ -412,6 +412,7 @@ typedef enum {\n MAN_NUMONYX,\n MAN_WINBOND,\n MAN_SST,\n+ MAN_ISSI,\n MAN_GENERIC,\n } Manufacturer;\n \n@@ -487,6 +488,8 @@ static inline Manufacturer get_man(Flash *s)\n return MAN_MACRONIX;\n case 0xBF:\n return MAN_SST;\n+ case 0x9D:\n+ return MAN_ISSI;\n default:\n return MAN_GENERIC;\n }\n@@ -706,6 +709,9 @@ static void complete_collecting_data(Flash *s)\n case MAN_SPANSION:\n s->quad_enable = !!(s->data[1] & 0x02);\n break;\n+ case MAN_ISSI:\n+ s->quad_enable = extract32(s->data[0], 6, 1);\n+ break;\n case MAN_MACRONIX:\n s->quad_enable = extract32(s->data[0], 6, 1);\n if (s->len > 1) {\n@@ -895,6 +901,19 @@ static void decode_fast_read_cmd(Flash *s)\n SPANSION_DUMMY_CLK_LEN\n );\n break;\n+ case MAN_ISSI:\n+ /*\n+ * The Fast Read instruction code is followed by address bytes and\n+ * dummy cycles, transmitted via the SI line.\n+ *\n+ * The number of dummy cycles is configurable but this is currently\n+ * unmodeled, hence the default value 8 is used.\n+ *\n+ * QPI (Quad Peripheral Interface) mode has different default value\n+ * of dummy cycles, but this is unsupported at the time being.\n+ */\n+ s->needed_bytes += 1;\n+ break;\n default:\n break;\n }\n@@ -934,6 +953,16 @@ static void decode_dio_read_cmd(Flash *s)\n break;\n }\n break;\n+ case MAN_ISSI:\n+ /*\n+ * The Fast Read Dual I/O instruction code is followed by address bytes\n+ * and dummy cycles, transmitted via the IO1 and IO0 line.\n+ *\n+ * The number of dummy cycles is configurable but this is currently\n+ * unmodeled, hence the default value 4 is used.\n+ */\n+ s->needed_bytes += 1;\n+ break;\n default:\n break;\n }\n@@ -974,6 +1003,19 @@ static void decode_qio_read_cmd(Flash *s)\n break;\n }\n break;\n+ case MAN_ISSI:\n+ /*\n+ * The Fast Read Quad I/O instruction code is followed by address bytes\n+ * and dummy cycles, transmitted via the IO3, IO2, IO1 and IO0 line.\n+ *\n+ * The number of dummy cycles is configurable but this is currently\n+ * unmodeled, hence the default value 6 is used.\n+ *\n+ * QPI (Quad Peripheral Interface) mode has different default value\n+ * of dummy cycles, but this is unsupported at the time being.\n+ */\n+ s->needed_bytes += 3;\n+ break;\n default:\n break;\n }\n@@ -1132,7 +1174,7 @@ static void decode_new_cmd(Flash *s, uint32_t value)\n \n case RDSR:\n s->data[0] = (!!s->write_enable) << 1;\n- if (get_man(s) == MAN_MACRONIX) {\n+ if (get_man(s) == MAN_MACRONIX || get_man(s) == MAN_ISSI) {\n s->data[0] |= (!!s->quad_enable) << 6;\n }\n if (get_man(s) == MAN_SST) {\n","prefixes":["PULL","v2","05/19"]}