{"id":1447385,"url":"http://patchwork.ozlabs.org/api/patches/1447385/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20210304144651.310037-10-alistair.francis@wdc.com/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20210304144651.310037-10-alistair.francis@wdc.com>","list_archive_url":null,"date":"2021-03-04T14:46:41","name":"[PULL,v2,09/19] hw/riscv: sifive_u: Add QSPI2 controller and connect an SD card","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"c0a41d4f3092dcab2e2675939de94c091a1e0854","submitter":{"id":74007,"url":"http://patchwork.ozlabs.org/api/people/74007/?format=json","name":"Alistair Francis","email":"alistair.francis@wdc.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20210304144651.310037-10-alistair.francis@wdc.com/mbox/","series":[{"id":232161,"url":"http://patchwork.ozlabs.org/api/series/232161/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=232161","date":"2021-03-04T14:46:33","name":"[PULL,v2,01/19] target/riscv: Declare csr_ops[] with a known size","version":2,"mbox":"http://patchwork.ozlabs.org/series/232161/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/1447385/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/1447385/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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d=\"scan'208\";a=\"271984416\"","WDCIronportException":"Internal","From":"Alistair Francis ","To":"peter.maydell@linaro.org","Subject":"[PULL v2 09/19] hw/riscv: sifive_u: Add QSPI2 controller and connect\n an SD card","Date":"Thu, 4 Mar 2021 09:46:41 -0500","Message-Id":"<20210304144651.310037-10-alistair.francis@wdc.com>","X-Mailer":"git-send-email 2.30.1","In-Reply-To":"<20210304144651.310037-1-alistair.francis@wdc.com>","References":"<20210304144651.310037-1-alistair.francis@wdc.com>","MIME-Version":"1.0","Content-Transfer-Encoding":"8bit","Received-SPF":"pass client-ip=68.232.141.245;\n envelope-from=prvs=690dc056c=alistair.francis@wdc.com;\n helo=esa1.hgst.iphmx.com","X-Spam_score_int":"-27","X-Spam_score":"-2.8","X-Spam_bar":"--","X-Spam_report":"(-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_PASS=-0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.23","Precedence":"list","List-Id":"","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Cc":"alistair23@gmail.com, Bin Meng ,\n Alistair Francis , qemu-devel@nongnu.org","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"\"Qemu-devel\"\n "},"content":"From: Bin Meng \n\nThis adds the QSPI2 controller to the SoC, and connects an SD\ncard to it. The generation of corresponding device tree source\nfragment is also added.\n\nSpecify machine property `msel` to 11 to boot the same upstream\nU-Boot SPL and payload image for the SiFive HiFive Unleashed board.\nNote subsequent payload is stored in the SD card image.\n\n$ qemu-system-riscv64 -nographic -M sifive_u,msel=11 -smp 5 -m 8G \\\n -bios u-boot-spl.bin -drive file=sdcard.img,if=sd\n\nSigned-off-by: Bin Meng \nReviewed-by: Alistair Francis \nMessage-id: 20210126060007.12904-6-bmeng.cn@gmail.com\nSigned-off-by: Alistair Francis \n---\n include/hw/riscv/sifive_u.h | 3 +++\n hw/riscv/sifive_u.c | 43 +++++++++++++++++++++++++++++++++++--\n hw/riscv/Kconfig | 1 +\n 3 files changed, 45 insertions(+), 2 deletions(-)","diff":"diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h\nindex 8824b7c031..de1464a2ce 100644\n--- a/include/hw/riscv/sifive_u.h\n+++ b/include/hw/riscv/sifive_u.h\n@@ -47,6 +47,7 @@ typedef struct SiFiveUSoCState {\n SiFiveUOTPState otp;\n SiFivePDMAState dma;\n SiFiveSPIState spi0;\n+ SiFiveSPIState spi2;\n CadenceGEMState gem;\n \n uint32_t serial;\n@@ -85,6 +86,7 @@ enum {\n SIFIVE_U_DEV_UART1,\n SIFIVE_U_DEV_GPIO,\n SIFIVE_U_DEV_QSPI0,\n+ SIFIVE_U_DEV_QSPI2,\n SIFIVE_U_DEV_OTP,\n SIFIVE_U_DEV_DMC,\n SIFIVE_U_DEV_FLASH0,\n@@ -99,6 +101,7 @@ enum {\n SIFIVE_U_L2CC_IRQ2 = 3,\n SIFIVE_U_UART0_IRQ = 4,\n SIFIVE_U_UART1_IRQ = 5,\n+ SIFIVE_U_QSPI2_IRQ = 6,\n SIFIVE_U_GPIO_IRQ0 = 7,\n SIFIVE_U_GPIO_IRQ1 = 8,\n SIFIVE_U_GPIO_IRQ2 = 9,\ndiff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c\nindex 43a0e983d2..6c1158a848 100644\n--- a/hw/riscv/sifive_u.c\n+++ b/hw/riscv/sifive_u.c\n@@ -16,6 +16,7 @@\n * 6) GEM (Gigabit Ethernet Controller) and management block\n * 7) DMA (Direct Memory Access Controller)\n * 8) SPI0 connected to an SPI flash\n+ * 9) SPI2 connected to an SD card\n *\n * This board currently generates devicetree dynamically that indicates at least\n * two harts and up to five harts.\n@@ -77,6 +78,7 @@ static const struct MemmapEntry {\n [SIFIVE_U_DEV_UART0] = { 0x10010000, 0x1000 },\n [SIFIVE_U_DEV_UART1] = { 0x10011000, 0x1000 },\n [SIFIVE_U_DEV_QSPI0] = { 0x10040000, 0x1000 },\n+ [SIFIVE_U_DEV_QSPI2] = { 0x10050000, 0x1000 },\n [SIFIVE_U_DEV_GPIO] = { 0x10060000, 0x1000 },\n [SIFIVE_U_DEV_OTP] = { 0x10070000, 0x1000 },\n [SIFIVE_U_DEV_GEM] = { 0x10090000, 0x2000 },\n@@ -345,6 +347,31 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,\n \"sifive,fu540-c000-ccache\");\n g_free(nodename);\n \n+ nodename = g_strdup_printf(\"/soc/spi@%lx\",\n+ (long)memmap[SIFIVE_U_DEV_QSPI2].base);\n+ qemu_fdt_add_subnode(fdt, nodename);\n+ qemu_fdt_setprop_cell(fdt, nodename, \"#size-cells\", 0);\n+ qemu_fdt_setprop_cell(fdt, nodename, \"#address-cells\", 1);\n+ qemu_fdt_setprop_cells(fdt, nodename, \"clocks\",\n+ prci_phandle, PRCI_CLK_TLCLK);\n+ qemu_fdt_setprop_cell(fdt, nodename, \"interrupts\", SIFIVE_U_QSPI2_IRQ);\n+ qemu_fdt_setprop_cell(fdt, nodename, \"interrupt-parent\", plic_phandle);\n+ qemu_fdt_setprop_cells(fdt, nodename, \"reg\",\n+ 0x0, memmap[SIFIVE_U_DEV_QSPI2].base,\n+ 0x0, memmap[SIFIVE_U_DEV_QSPI2].size);\n+ qemu_fdt_setprop_string(fdt, nodename, \"compatible\", \"sifive,spi0\");\n+ g_free(nodename);\n+\n+ nodename = g_strdup_printf(\"/soc/spi@%lx/mmc@0\",\n+ (long)memmap[SIFIVE_U_DEV_QSPI2].base);\n+ qemu_fdt_add_subnode(fdt, nodename);\n+ qemu_fdt_setprop(fdt, nodename, \"disable-wp\", NULL, 0);\n+ qemu_fdt_setprop_cells(fdt, nodename, \"voltage-ranges\", 3300, 3300);\n+ qemu_fdt_setprop_cell(fdt, nodename, \"spi-max-frequency\", 20000000);\n+ qemu_fdt_setprop_cell(fdt, nodename, \"reg\", 0);\n+ qemu_fdt_setprop_string(fdt, nodename, \"compatible\", \"mmc-spi-slot\");\n+ g_free(nodename);\n+\n nodename = g_strdup_printf(\"/soc/spi@%lx\",\n (long)memmap[SIFIVE_U_DEV_QSPI0].base);\n qemu_fdt_add_subnode(fdt, nodename);\n@@ -469,8 +496,8 @@ static void sifive_u_machine_init(MachineState *machine)\n uint32_t fdt_load_addr;\n uint64_t kernel_entry;\n DriveInfo *dinfo;\n- DeviceState *flash_dev;\n- qemu_irq flash_cs;\n+ DeviceState *flash_dev, *sd_dev;\n+ qemu_irq flash_cs, sd_cs;\n \n /* Initialize SoC */\n object_initialize_child(OBJECT(machine), \"soc\", &s->soc, TYPE_RISCV_U_SOC);\n@@ -616,6 +643,12 @@ static void sifive_u_machine_init(MachineState *machine)\n \n flash_cs = qdev_get_gpio_in_named(flash_dev, SSI_GPIO_CS, 0);\n sysbus_connect_irq(SYS_BUS_DEVICE(&s->soc.spi0), 1, flash_cs);\n+\n+ /* Connect an SD card to SPI2 */\n+ sd_dev = ssi_create_peripheral(s->soc.spi2.spi, \"ssi-sd\");\n+\n+ sd_cs = qdev_get_gpio_in_named(sd_dev, SSI_GPIO_CS, 0);\n+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->soc.spi2), 1, sd_cs);\n }\n \n static bool sifive_u_machine_get_start_in_flash(Object *obj, Error **errp)\n@@ -726,6 +759,7 @@ static void sifive_u_soc_instance_init(Object *obj)\n object_initialize_child(obj, \"gpio\", &s->gpio, TYPE_SIFIVE_GPIO);\n object_initialize_child(obj, \"pdma\", &s->dma, TYPE_SIFIVE_PDMA);\n object_initialize_child(obj, \"spi0\", &s->spi0, TYPE_SIFIVE_SPI);\n+ object_initialize_child(obj, \"spi2\", &s->spi2, TYPE_SIFIVE_SPI);\n }\n \n static void sifive_u_soc_realize(DeviceState *dev, Error **errp)\n@@ -879,6 +913,11 @@ static void sifive_u_soc_realize(DeviceState *dev, Error **errp)\n memmap[SIFIVE_U_DEV_QSPI0].base);\n sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi0), 0,\n qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_QSPI0_IRQ));\n+ sysbus_realize(SYS_BUS_DEVICE(&s->spi2), errp);\n+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi2), 0,\n+ memmap[SIFIVE_U_DEV_QSPI2].base);\n+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi2), 0,\n+ qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_QSPI2_IRQ));\n }\n \n static Property sifive_u_soc_props[] = {\ndiff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig\nindex 6330297b4e..d139074b02 100644\n--- a/hw/riscv/Kconfig\n+++ b/hw/riscv/Kconfig\n@@ -57,6 +57,7 @@ config SIFIVE_U\n select SIFIVE_U_OTP\n select SIFIVE_U_PRCI\n select SSI_M25P80\n+ select SSI_SD\n select UNIMP\n \n config SPIKE\n","prefixes":["PULL","v2","09/19"]}