{"id":1447384,"url":"http://patchwork.ozlabs.org/api/patches/1447384/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20210304144651.310037-5-alistair.francis@wdc.com/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20210304144651.310037-5-alistair.francis@wdc.com>","list_archive_url":null,"date":"2021-03-04T14:46:36","name":"[PULL,v2,04/19] target-riscv: support QMP dump-guest-memory","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"9b0939d126d87050988125ea55fe81ed33fbf5cf","submitter":{"id":74007,"url":"http://patchwork.ozlabs.org/api/people/74007/?format=json","name":"Alistair Francis","email":"alistair.francis@wdc.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20210304144651.310037-5-alistair.francis@wdc.com/mbox/","series":[{"id":232161,"url":"http://patchwork.ozlabs.org/api/series/232161/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=232161","date":"2021-03-04T14:46:33","name":"[PULL,v2,01/19] target/riscv: Declare csr_ops[] with a known size","version":2,"mbox":"http://patchwork.ozlabs.org/series/232161/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/1447384/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/1447384/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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d=\"scan'208\";a=\"271984402\"","WDCIronportException":"Internal","From":"Alistair Francis ","To":"peter.maydell@linaro.org","Subject":"[PULL v2 04/19] target-riscv: support QMP dump-guest-memory","Date":"Thu, 4 Mar 2021 09:46:36 -0500","Message-Id":"<20210304144651.310037-5-alistair.francis@wdc.com>","X-Mailer":"git-send-email 2.30.1","In-Reply-To":"<20210304144651.310037-1-alistair.francis@wdc.com>","References":"<20210304144651.310037-1-alistair.francis@wdc.com>","MIME-Version":"1.0","Content-Transfer-Encoding":"8bit","Received-SPF":"pass client-ip=68.232.141.245;\n envelope-from=prvs=690dc056c=alistair.francis@wdc.com;\n helo=esa1.hgst.iphmx.com","X-Spam_score_int":"-27","X-Spam_score":"-2.8","X-Spam_bar":"--","X-Spam_report":"(-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_PASS=-0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.23","Precedence":"list","List-Id":"","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Cc":"Andrew Jones , Mingwang Li ,\n Palmer Dabbelt , qemu-devel@nongnu.org,\n Alistair Francis , alistair23@gmail.com,\n Yifei Jiang ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"\"Qemu-devel\"\n "},"content":"From: Yifei Jiang \n\nAdd the support needed for creating prstatus elf notes. This allows\nus to use QMP dump-guest-memory.\n\nNow ELF notes of RISC-V only contain prstatus elf notes.\n\nSigned-off-by: Yifei Jiang \nSigned-off-by: Mingwang Li \nReviewed-by: Alistair Francis \nReviewed-by: Andrew Jones \nReviewed-by: Palmer Dabbelt \nMessage-id: 20210201124458.1248-2-jiangyifei@huawei.com\nSigned-off-by: Alistair Francis \n---\n target/riscv/cpu.h | 4 +\n target/riscv/cpu_bits.h | 1 +\n target/riscv/arch_dump.c | 202 +++++++++++++++++++++++++++++++++++++++\n target/riscv/cpu.c | 2 +\n target/riscv/meson.build | 1 +\n 5 files changed, 210 insertions(+)\n create mode 100644 target/riscv/arch_dump.c","diff":"diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h\nindex 419a21478c..0edb2826a2 100644\n--- a/target/riscv/cpu.h\n+++ b/target/riscv/cpu.h\n@@ -323,6 +323,10 @@ extern const char * const riscv_intr_names[];\n \n const char *riscv_cpu_get_trap_name(target_ulong cause, bool async);\n void riscv_cpu_do_interrupt(CPUState *cpu);\n+int riscv_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs,\n+ int cpuid, void *opaque);\n+int riscv_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs,\n+ int cpuid, void *opaque);\n int riscv_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);\n int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);\n bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request);\ndiff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h\nindex 4196ef8b69..caf4599207 100644\n--- a/target/riscv/cpu_bits.h\n+++ b/target/riscv/cpu_bits.h\n@@ -368,6 +368,7 @@\n #define MSTATUS_MIE 0x00000008\n #define MSTATUS_UPIE 0x00000010\n #define MSTATUS_SPIE 0x00000020\n+#define MSTATUS_UBE 0x00000040\n #define MSTATUS_MPIE 0x00000080\n #define MSTATUS_SPP 0x00000100\n #define MSTATUS_MPP 0x00001800\ndiff --git a/target/riscv/arch_dump.c b/target/riscv/arch_dump.c\nnew file mode 100644\nindex 0000000000..709f621d82\n--- /dev/null\n+++ b/target/riscv/arch_dump.c\n@@ -0,0 +1,202 @@\n+/* Support for writing ELF notes for RISC-V architectures\n+ *\n+ * Copyright (C) 2021 Huawei Technologies Co., Ltd\n+ *\n+ * This program is free software; you can redistribute it and/or modify it\n+ * under the terms and conditions of the GNU General Public License,\n+ * version 2 or later, as published by the Free Software Foundation.\n+ *\n+ * This program is distributed in the hope it will be useful, but WITHOUT\n+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n+ * more details.\n+ *\n+ * You should have received a copy of the GNU General Public License along with\n+ * this program. If not, see .\n+ */\n+\n+#include \"qemu/osdep.h\"\n+#include \"cpu.h\"\n+#include \"elf.h\"\n+#include \"sysemu/dump.h\"\n+\n+/* struct user_regs_struct from arch/riscv/include/uapi/asm/ptrace.h */\n+struct riscv64_user_regs {\n+ uint64_t pc;\n+ uint64_t regs[31];\n+} QEMU_PACKED;\n+\n+QEMU_BUILD_BUG_ON(sizeof(struct riscv64_user_regs) != 256);\n+\n+/* struct elf_prstatus from include/linux/elfcore.h */\n+struct riscv64_elf_prstatus {\n+ char pad1[32]; /* 32 == offsetof(struct elf_prstatus, pr_pid) */\n+ uint32_t pr_pid;\n+ char pad2[76]; /* 76 == offsetof(struct elf_prstatus, pr_reg) -\n+ offsetof(struct elf_prstatus, pr_ppid) */\n+ struct riscv64_user_regs pr_reg;\n+ char pad3[8];\n+} QEMU_PACKED;\n+\n+QEMU_BUILD_BUG_ON(sizeof(struct riscv64_elf_prstatus) != 376);\n+\n+struct riscv64_note {\n+ Elf64_Nhdr hdr;\n+ char name[8]; /* align_up(sizeof(\"CORE\"), 4) */\n+ struct riscv64_elf_prstatus prstatus;\n+} QEMU_PACKED;\n+\n+#define RISCV64_NOTE_HEADER_SIZE offsetof(struct riscv64_note, prstatus)\n+#define RISCV64_PRSTATUS_NOTE_SIZE \\\n+ (RISCV64_NOTE_HEADER_SIZE + sizeof(struct riscv64_elf_prstatus))\n+\n+static void riscv64_note_init(struct riscv64_note *note, DumpState *s,\n+ const char *name, Elf64_Word namesz,\n+ Elf64_Word type, Elf64_Word descsz)\n+{\n+ memset(note, 0, sizeof(*note));\n+\n+ note->hdr.n_namesz = cpu_to_dump32(s, namesz);\n+ note->hdr.n_descsz = cpu_to_dump32(s, descsz);\n+ note->hdr.n_type = cpu_to_dump32(s, type);\n+\n+ memcpy(note->name, name, namesz);\n+}\n+\n+int riscv_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs,\n+ int cpuid, void *opaque)\n+{\n+ struct riscv64_note note;\n+ RISCVCPU *cpu = RISCV_CPU(cs);\n+ CPURISCVState *env = &cpu->env;\n+ DumpState *s = opaque;\n+ int ret, i = 0;\n+ const char name[] = \"CORE\";\n+\n+ riscv64_note_init(¬e, s, name, sizeof(name),\n+ NT_PRSTATUS, sizeof(note.prstatus));\n+\n+ note.prstatus.pr_pid = cpu_to_dump32(s, cpuid);\n+\n+ note.prstatus.pr_reg.pc = cpu_to_dump64(s, env->pc);\n+\n+ for (i = 0; i < 31; i++) {\n+ note.prstatus.pr_reg.regs[i] = cpu_to_dump64(s, env->gpr[i + 1]);\n+ }\n+\n+ ret = f(¬e, RISCV64_PRSTATUS_NOTE_SIZE, s);\n+ if (ret < 0) {\n+ return -1;\n+ }\n+\n+ return ret;\n+}\n+\n+struct riscv32_user_regs {\n+ uint32_t pc;\n+ uint32_t regs[31];\n+} QEMU_PACKED;\n+\n+QEMU_BUILD_BUG_ON(sizeof(struct riscv32_user_regs) != 128);\n+\n+struct riscv32_elf_prstatus {\n+ char pad1[24]; /* 24 == offsetof(struct elf_prstatus, pr_pid) */\n+ uint32_t pr_pid;\n+ char pad2[44]; /* 44 == offsetof(struct elf_prstatus, pr_reg) -\n+ offsetof(struct elf_prstatus, pr_ppid) */\n+ struct riscv32_user_regs pr_reg;\n+ char pad3[4];\n+} QEMU_PACKED;\n+\n+QEMU_BUILD_BUG_ON(sizeof(struct riscv32_elf_prstatus) != 204);\n+\n+struct riscv32_note {\n+ Elf32_Nhdr hdr;\n+ char name[8]; /* align_up(sizeof(\"CORE\"), 4) */\n+ struct riscv32_elf_prstatus prstatus;\n+} QEMU_PACKED;\n+\n+#define RISCV32_NOTE_HEADER_SIZE offsetof(struct riscv32_note, prstatus)\n+#define RISCV32_PRSTATUS_NOTE_SIZE \\\n+ (RISCV32_NOTE_HEADER_SIZE + sizeof(struct riscv32_elf_prstatus))\n+\n+static void riscv32_note_init(struct riscv32_note *note, DumpState *s,\n+ const char *name, Elf32_Word namesz,\n+ Elf32_Word type, Elf32_Word descsz)\n+{\n+ memset(note, 0, sizeof(*note));\n+\n+ note->hdr.n_namesz = cpu_to_dump32(s, namesz);\n+ note->hdr.n_descsz = cpu_to_dump32(s, descsz);\n+ note->hdr.n_type = cpu_to_dump32(s, type);\n+\n+ memcpy(note->name, name, namesz);\n+}\n+\n+int riscv_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs,\n+ int cpuid, void *opaque)\n+{\n+ struct riscv32_note note;\n+ RISCVCPU *cpu = RISCV_CPU(cs);\n+ CPURISCVState *env = &cpu->env;\n+ DumpState *s = opaque;\n+ int ret, i;\n+ const char name[] = \"CORE\";\n+\n+ riscv32_note_init(¬e, s, name, sizeof(name),\n+ NT_PRSTATUS, sizeof(note.prstatus));\n+\n+ note.prstatus.pr_pid = cpu_to_dump32(s, cpuid);\n+\n+ note.prstatus.pr_reg.pc = cpu_to_dump32(s, env->pc);\n+\n+ for (i = 0; i < 31; i++) {\n+ note.prstatus.pr_reg.regs[i] = cpu_to_dump32(s, env->gpr[i + 1]);\n+ }\n+\n+ ret = f(¬e, RISCV32_PRSTATUS_NOTE_SIZE, s);\n+ if (ret < 0) {\n+ return -1;\n+ }\n+\n+ return ret;\n+}\n+\n+int cpu_get_dump_info(ArchDumpInfo *info,\n+ const GuestPhysBlockList *guest_phys_blocks)\n+{\n+ RISCVCPU *cpu;\n+ CPURISCVState *env;\n+\n+ if (first_cpu == NULL) {\n+ return -1;\n+ }\n+ cpu = RISCV_CPU(first_cpu);\n+ env = &cpu->env;\n+\n+ info->d_machine = EM_RISCV;\n+\n+#if defined(TARGET_RISCV64)\n+ info->d_class = ELFCLASS64;\n+#else\n+ info->d_class = ELFCLASS32;\n+#endif\n+\n+ info->d_endian = (env->mstatus & MSTATUS_UBE) != 0\n+ ? ELFDATA2MSB : ELFDATA2LSB;\n+\n+ return 0;\n+}\n+\n+ssize_t cpu_get_note_size(int class, int machine, int nr_cpus)\n+{\n+ size_t note_size;\n+\n+ if (class == ELFCLASS64) {\n+ note_size = RISCV64_PRSTATUS_NOTE_SIZE;\n+ } else {\n+ note_size = RISCV32_PRSTATUS_NOTE_SIZE;\n+ }\n+\n+ return note_size * nr_cpus;\n+}\ndiff --git a/target/riscv/cpu.c b/target/riscv/cpu.c\nindex 16f1a34238..ddea8fbeeb 100644\n--- a/target/riscv/cpu.c\n+++ b/target/riscv/cpu.c\n@@ -624,6 +624,8 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data)\n cc->get_phys_page_debug = riscv_cpu_get_phys_page_debug;\n /* For now, mark unmigratable: */\n cc->vmsd = &vmstate_riscv_cpu;\n+ cc->write_elf64_note = riscv_cpu_write_elf64_note;\n+ cc->write_elf32_note = riscv_cpu_write_elf32_note;\n #endif\n cc->gdb_arch_name = riscv_gdb_arch_name;\n cc->gdb_get_dynamic_xml = riscv_gdb_get_dynamic_xml;\ndiff --git a/target/riscv/meson.build b/target/riscv/meson.build\nindex 14a5c62dac..88ab850682 100644\n--- a/target/riscv/meson.build\n+++ b/target/riscv/meson.build\n@@ -26,6 +26,7 @@ riscv_ss.add(files(\n \n riscv_softmmu_ss = ss.source_set()\n riscv_softmmu_ss.add(files(\n+ 'arch_dump.c',\n 'pmp.c',\n 'monitor.c',\n 'machine.c'\n","prefixes":["PULL","v2","04/19"]}