{"id":1447377,"url":"http://patchwork.ozlabs.org/api/patches/1447377/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20210304144651.310037-2-alistair.francis@wdc.com/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20210304144651.310037-2-alistair.francis@wdc.com>","list_archive_url":null,"date":"2021-03-04T14:46:33","name":"[PULL,v2,01/19] target/riscv: Declare csr_ops[] with a known size","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"c576ca9421bcbbf44133157bde4dedefbf4b5a89","submitter":{"id":74007,"url":"http://patchwork.ozlabs.org/api/people/74007/?format=json","name":"Alistair Francis","email":"alistair.francis@wdc.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20210304144651.310037-2-alistair.francis@wdc.com/mbox/","series":[{"id":232161,"url":"http://patchwork.ozlabs.org/api/series/232161/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=232161","date":"2021-03-04T14:46:33","name":"[PULL,v2,01/19] target/riscv: Declare csr_ops[] with a known size","version":2,"mbox":"http://patchwork.ozlabs.org/series/232161/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/1447377/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/1447377/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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d=\"scan'208\";a=\"265660838\"","WDCIronportException":"Internal","From":"Alistair Francis ","To":"peter.maydell@linaro.org","Subject":"[PULL v2 01/19] target/riscv: Declare csr_ops[] with a known size","Date":"Thu, 4 Mar 2021 09:46:33 -0500","Message-Id":"<20210304144651.310037-2-alistair.francis@wdc.com>","X-Mailer":"git-send-email 2.30.1","In-Reply-To":"<20210304144651.310037-1-alistair.francis@wdc.com>","References":"<20210304144651.310037-1-alistair.francis@wdc.com>","MIME-Version":"1.0","Content-Type":"text/plain; charset=UTF-8","Content-Transfer-Encoding":"8bit","Received-SPF":"pass client-ip=68.232.143.124;\n envelope-from=prvs=690dc056c=alistair.francis@wdc.com;\n helo=esa2.hgst.iphmx.com","X-Spam_score_int":"-43","X-Spam_score":"-4.4","X-Spam_bar":"----","X-Spam_report":"(-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.23","Precedence":"list","List-Id":"","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Cc":"alistair23@gmail.com, Bin Meng ,\n Alistair Francis , qemu-devel@nongnu.org,\n\t=?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"\"Qemu-devel\"\n "},"content":"From: Bin Meng \n\ncsr_ops[] is currently declared with an unknown size in cpu.h.\nSince the array size is known, let's do a complete declaration.\n\nSigned-off-by: Bin Meng \nReviewed-by: Philippe Mathieu-Daudé \nReviewed-by: Alistair Francis \nMessage-id: 1611024723-14293-1-git-send-email-bmeng.cn@gmail.com\nSigned-off-by: Alistair Francis \n---\n target/riscv/cpu.h | 2 +-\n 1 file changed, 1 insertion(+), 1 deletion(-)","diff":"diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h\nindex 02758ae0eb..419a21478c 100644\n--- a/target/riscv/cpu.h\n+++ b/target/riscv/cpu.h\n@@ -487,7 +487,7 @@ enum {\n };\n \n /* CSR function table */\n-extern riscv_csr_operations csr_ops[];\n+extern riscv_csr_operations csr_ops[CSR_TABLE_SIZE];\n \n void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops);\n void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops);\n","prefixes":["PULL","v2","01/19"]}