{"id":1117708,"url":"http://patchwork.ozlabs.org/api/patches/1117708/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-gpio/patch/1560843991-24123-2-git-send-email-skomatineni@nvidia.com/","project":{"id":42,"url":"http://patchwork.ozlabs.org/api/projects/42/?format=json","name":"Linux GPIO development","link_name":"linux-gpio","list_id":"linux-gpio.vger.kernel.org","list_email":"linux-gpio@vger.kernel.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<1560843991-24123-2-git-send-email-skomatineni@nvidia.com>","list_archive_url":null,"date":"2019-06-18T07:46:15","name":"[V3,01/17] irqchip: tegra: do not disable COP IRQ during suspend","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"eb0563091536b7ef1e2a341e901308bb238f18e4","submitter":{"id":75554,"url":"http://patchwork.ozlabs.org/api/people/75554/?format=json","name":"Sowjanya Komatineni","email":"skomatineni@nvidia.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/linux-gpio/patch/1560843991-24123-2-git-send-email-skomatineni@nvidia.com/mbox/","series":[{"id":114436,"url":"http://patchwork.ozlabs.org/api/series/114436/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-gpio/list/?series=114436","date":"2019-06-18T07:46:16","name":"SC7 entry and exit support for Tegra210","version":3,"mbox":"http://patchwork.ozlabs.org/series/114436/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/1117708/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/1117708/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=linux-gpio-owner@vger.kernel.org;\n\treceiver=)","ozlabs.org;\n\tdmarc=pass (p=none dis=none) header.from=nvidia.com","ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=nvidia.com header.i=@nvidia.com\n\theader.b=\"py24H3zS\"; dkim-atps=neutral"],"Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 45SgDk6tkNz9s9y\n\tfor ;\n\tTue, 18 Jun 2019 17:48:22 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1728527AbfFRHqk (ORCPT );\n\tTue, 18 Jun 2019 03:46:40 -0400","from hqemgate16.nvidia.com ([216.228.121.65]:14088 \"EHLO\n\thqemgate16.nvidia.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1725870AbfFRHqj (ORCPT\n\t); Tue, 18 Jun 2019 03:46:39 -0400","from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by\n\thqemgate16.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA)\n\tid ; Tue, 18 Jun 2019 00:46:38 -0700","from hqmail.nvidia.com ([172.20.161.6])\n\tby hqpgpgate102.nvidia.com (PGP Universal service);\n\tTue, 18 Jun 2019 00:46:38 -0700","from HQMAIL105.nvidia.com (172.20.187.12) by HQMAIL101.nvidia.com\n\t(172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1473.3;\n\tTue, 18 Jun 2019 07:46:38 +0000","from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL105.nvidia.com\n\t(172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via\n\tFrontend Transport; Tue, 18 Jun 2019 07:46:37 +0000","from skomatineni-linux.nvidia.com (Not Verified[10.2.168.217]) by\n\thqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121)\n\tid ; Tue, 18 Jun 2019 00:46:37 -0700"],"X-PGP-Universal":"processed;\n\tby hqpgpgate102.nvidia.com on Tue, 18 Jun 2019 00:46:38 -0700","From":"Sowjanya Komatineni ","To":", ,\n\t, ,\n\t, ,\n\t, ","CC":", ,\n\t, ,\n\t, ,\n\t, , ,\n\t, ,\n\t, , ,\n\t, ","Subject":"[PATCH V3 01/17] irqchip: tegra: do not disable COP IRQ during\n\tsuspend","Date":"Tue, 18 Jun 2019 00:46:15 -0700","Message-ID":"<1560843991-24123-2-git-send-email-skomatineni@nvidia.com>","X-Mailer":"git-send-email 2.7.4","In-Reply-To":"<1560843991-24123-1-git-send-email-skomatineni@nvidia.com>","References":"<1560843991-24123-1-git-send-email-skomatineni@nvidia.com>","X-NVConfidentiality":"public","MIME-Version":"1.0","Content-Type":"text/plain","DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1;\n\tt=1560843998; bh=tvQslV53EocwPwpfbzGR9nKs+VHwI0rTa6hb/3PMnzs=;\n\th=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer:\n\tIn-Reply-To:References:X-NVConfidentiality:MIME-Version:\n\tContent-Type;\n\tb=py24H3zSsCh8vv5XIuecFN8vBKIfcKLB9Ef4V5fvur/MzQXWl45QCvRxP818KqWxE\n\tinVizr59zaN7EAtq0t8/39FeJskarrLcpFdSdIFHFPmdoA2Bf9hfw6unz+MQDYFvwW\n\t+WOPoYER0cGVRSL9W81Xd8bgyvk39dlZG/uszlhYKJvMxBDdoTZ+5fvvr3aiHWSdVW\n\tTr3CPVztngIOsXKPv8bkMgmUy8e/5NK0EaDwJKXYB0sSfRc/Utfsyn+M4BCfLb1XIE\n\tv02mIC4XkH2pyCNoM5hIC94oH85917Upn0Wrn186s9hIPfG++kEMiOlNLnh0/xSYgr\n\t43UaYgdmjEgnQ==","Sender":"linux-gpio-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"linux-gpio@vger.kernel.org"},"content":"Tegra210 platforms use sc7 entry firmware to program Tegra LP0/SC7 entry\nsequence and sc7 entry firmware is run from COP/BPMP-Lite.\n\nSo, COP/BPMP-Lite still need IRQ function to finish SC7 suspend sequence\nfor Tegra210.\n\nThis patch has fix for leaving the COP IRQ enabled for Tegra210 during\ninterrupt controller suspend operation.\n\nSigned-off-by: Sowjanya Komatineni \n---\n drivers/irqchip/irq-tegra.c | 21 +++++++++++++++++++--\n 1 file changed, 19 insertions(+), 2 deletions(-)","diff":"diff --git a/drivers/irqchip/irq-tegra.c b/drivers/irqchip/irq-tegra.c\nindex e1f771c72fc4..cf0c07052064 100644\n--- a/drivers/irqchip/irq-tegra.c\n+++ b/drivers/irqchip/irq-tegra.c\n@@ -44,18 +44,22 @@ static unsigned int num_ictlrs;\n \n struct tegra_ictlr_soc {\n \tunsigned int num_ictlrs;\n+\tbool supports_sc7;\n };\n \n static const struct tegra_ictlr_soc tegra20_ictlr_soc = {\n \t.num_ictlrs = 4,\n+\t.supports_sc7 = false,\n };\n \n static const struct tegra_ictlr_soc tegra30_ictlr_soc = {\n \t.num_ictlrs = 5,\n+\t.supports_sc7 = false,\n };\n \n static const struct tegra_ictlr_soc tegra210_ictlr_soc = {\n \t.num_ictlrs = 6,\n+\t.supports_sc7 = true,\n };\n \n static const struct of_device_id ictlr_matches[] = {\n@@ -67,6 +71,7 @@ static const struct of_device_id ictlr_matches[] = {\n \n struct tegra_ictlr_info {\n \tvoid __iomem *base[TEGRA_MAX_NUM_ICTLRS];\n+\tconst struct tegra_ictlr_soc *soc;\n #ifdef CONFIG_PM_SLEEP\n \tu32 cop_ier[TEGRA_MAX_NUM_ICTLRS];\n \tu32 cop_iep[TEGRA_MAX_NUM_ICTLRS];\n@@ -147,8 +152,19 @@ static int tegra_ictlr_suspend(void)\n \t\tlic->cop_ier[i] = readl_relaxed(ictlr + ICTLR_COP_IER);\n \t\tlic->cop_iep[i] = readl_relaxed(ictlr + ICTLR_COP_IEP_CLASS);\n \n-\t\t/* Disable COP interrupts */\n-\t\twritel_relaxed(~0ul, ictlr + ICTLR_COP_IER_CLR);\n+\t\t/*\n+\t\t * AVP/COP/BPMP-Lite is the Tegra boot processor.\n+\t\t *\n+\t\t * Tegra210 system suspend flow uses sc7entry firmware which\n+\t\t * is executed by COP/BPMP and it includes disabling COP IRQ,\n+\t\t * clamping CPU rail, turning off VDD_CPU, and preparing the\n+\t\t * system to go to SC7/LP0.\n+\t\t *\n+\t\t * COP/BPMP wakes up when COP IRQ is triggered and runs\n+\t\t * sc7entry-firmware. So need to keep COP interrupt enabled.\n+\t\t */\n+\t\tif (!lic->soc->supports_sc7)\n+\t\t\twritel_relaxed(~0ul, ictlr + ICTLR_COP_IER_CLR);\n \n \t\t/* Disable CPU interrupts */\n \t\twritel_relaxed(~0ul, ictlr + ICTLR_CPU_IER_CLR);\n@@ -339,6 +355,7 @@ static int __init tegra_ictlr_init(struct device_node *node,\n \t\tgoto out_unmap;\n \t}\n \n+\tlic->soc = soc;\n \ttegra_ictlr_syscore_init();\n \n \tpr_info(\"%pOF: %d interrupts forwarded to %pOF\\n\",\n","prefixes":["V3","01/17"]}