{"id":1117685,"url":"http://patchwork.ozlabs.org/api/patches/1117685/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-gpio/patch/1560843991-24123-14-git-send-email-skomatineni@nvidia.com/","project":{"id":42,"url":"http://patchwork.ozlabs.org/api/projects/42/?format=json","name":"Linux GPIO development","link_name":"linux-gpio","list_id":"linux-gpio.vger.kernel.org","list_email":"linux-gpio@vger.kernel.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<1560843991-24123-14-git-send-email-skomatineni@nvidia.com>","list_archive_url":null,"date":"2019-06-18T07:46:27","name":"[V3,13/17] soc/tegra: pmc: add pmc wake support for tegra210","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"5bd7db66f4b713300c17b19c2b4f1e9acf2f0607","submitter":{"id":75554,"url":"http://patchwork.ozlabs.org/api/people/75554/?format=json","name":"Sowjanya Komatineni","email":"skomatineni@nvidia.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/linux-gpio/patch/1560843991-24123-14-git-send-email-skomatineni@nvidia.com/mbox/","series":[{"id":114436,"url":"http://patchwork.ozlabs.org/api/series/114436/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-gpio/list/?series=114436","date":"2019-06-18T07:46:16","name":"SC7 entry and exit support for Tegra210","version":3,"mbox":"http://patchwork.ozlabs.org/series/114436/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/1117685/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/1117685/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=linux-gpio-owner@vger.kernel.org;\n\treceiver=)","ozlabs.org;\n\tdmarc=pass (p=none dis=none) header.from=nvidia.com","ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=nvidia.com header.i=@nvidia.com\n\theader.b=\"mr95d6Nt\"; dkim-atps=neutral"],"Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 45SgCv17Lsz9s4V\n\tfor ;\n\tTue, 18 Jun 2019 17:47:39 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1729140AbfFRHrL (ORCPT );\n\tTue, 18 Jun 2019 03:47:11 -0400","from hqemgate16.nvidia.com ([216.228.121.65]:14174 \"EHLO\n\thqemgate16.nvidia.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1726238AbfFRHrL (ORCPT\n\t); Tue, 18 Jun 2019 03:47:11 -0400","from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by\n\thqemgate16.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA)\n\tid ; Tue, 18 Jun 2019 00:47:09 -0700","from hqmail.nvidia.com ([172.20.161.6])\n\tby hqpgpgate101.nvidia.com (PGP Universal service);\n\tTue, 18 Jun 2019 00:47:09 -0700","from HQMAIL107.nvidia.com (172.20.187.13) by HQMAIL104.nvidia.com\n\t(172.18.146.11) with Microsoft SMTP Server (TLS) id 15.0.1473.3;\n\tTue, 18 Jun 2019 07:47:09 +0000","from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL107.nvidia.com\n\t(172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via\n\tFrontend Transport; Tue, 18 Jun 2019 07:47:09 +0000","from skomatineni-linux.nvidia.com (Not Verified[10.2.168.217]) by\n\thqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121)\n\tid ; Tue, 18 Jun 2019 00:47:09 -0700"],"X-PGP-Universal":"processed;\n\tby hqpgpgate101.nvidia.com on Tue, 18 Jun 2019 00:47:09 -0700","From":"Sowjanya Komatineni ","To":", ,\n\t, ,\n\t, ,\n\t, ","CC":", ,\n\t, ,\n\t, ,\n\t, , ,\n\t, ,\n\t, , ,\n\t, ","Subject":"[PATCH V3 13/17] soc/tegra: pmc: add pmc wake support for tegra210","Date":"Tue, 18 Jun 2019 00:46:27 -0700","Message-ID":"<1560843991-24123-14-git-send-email-skomatineni@nvidia.com>","X-Mailer":"git-send-email 2.7.4","In-Reply-To":"<1560843991-24123-1-git-send-email-skomatineni@nvidia.com>","References":"<1560843991-24123-1-git-send-email-skomatineni@nvidia.com>","X-NVConfidentiality":"public","MIME-Version":"1.0","Content-Type":"text/plain","DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1;\n\tt=1560844029; bh=Eft9jVTETH16qx1GufxFmbqLBke4vXfKbSmLNuCeeYA=;\n\th=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer:\n\tIn-Reply-To:References:X-NVConfidentiality:MIME-Version:\n\tContent-Type;\n\tb=mr95d6NtTmSciq2E3sFgyuSs+AhtQluFR6xuZePLQKADK7dnFg7ubCDF+Z2ECmrDj\n\ttiqISvbLEDLwsENrnRN6bHwv6R0mmB+5gkrDEKGfBjxrVA5xlvb2VvluZF4oZbFme6\n\tu8Mhyqfi9WkwGim+JaMdUHoualURPduJdvpevE4GdDUlj8V74Aa9M16tLg1q2+Vo4r\n\tC88q5Rrv6HvtnYRbS/w9nJY76eKcH/Uk8NN1bVnRezarg45uLwSoG4PJ4k9HyEKO6m\n\tzLb362kFexWJ270V/DFFj5YuFRA1qU8GUKDFHS/mNeqx0ZVnwet54Q0OVO1djAT2M3\n\twwJcPfytCj46A==","Sender":"linux-gpio-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"linux-gpio@vger.kernel.org"},"content":"This patch implements PMC wakeup sequence for Tegra210 and defines\ncommon used RTC alarm wake event.\n\nSigned-off-by: Sowjanya Komatineni \n---\n drivers/soc/tegra/pmc.c | 111 ++++++++++++++++++++++++++++++++++++++++++++++++\n 1 file changed, 111 insertions(+)","diff":"diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c\nindex e87f29a35fcf..603fc3bd73f5 100644\n--- a/drivers/soc/tegra/pmc.c\n+++ b/drivers/soc/tegra/pmc.c\n@@ -57,6 +57,12 @@\n #define PMC_CNTRL_SYSCLK_OE\t\tBIT(11) /* system clock enable */\n #define PMC_CNTRL_SYSCLK_POLARITY\tBIT(10) /* sys clk polarity */\n #define PMC_CNTRL_MAIN_RST\t\tBIT(4)\n+#define PMC_CNTRL_LATCH_WAKEUPS\tBIT(5)\n+\n+#define PMC_WAKE_MASK\t\t\t0x0c\n+#define PMC_WAKE_LEVEL\t\t\t0x10\n+#define PMC_WAKE_STATUS\t\t\t0x14\n+#define PMC_SW_WAKE_STATUS\t\t0x18\n \n #define DPD_SAMPLE\t\t\t0x020\n #define DPD_SAMPLE_ENABLE\t\tBIT(0)\n@@ -87,6 +93,11 @@\n \n #define PMC_SCRATCH41\t\t\t0x140\n \n+#define PMC_WAKE2_MASK\t\t\t0x160\n+#define PMC_WAKE2_LEVEL\t\t\t0x164\n+#define PMC_WAKE2_STATUS\t\t0x168\n+#define PMC_SW_WAKE2_STATUS\t\t0x16c\n+\n #define PMC_SENSOR_CTRL\t\t\t0x1b0\n #define PMC_SENSOR_CTRL_SCRATCH_WRITE\tBIT(2)\n #define PMC_SENSOR_CTRL_ENABLE_RST\tBIT(1)\n@@ -1921,6 +1932,55 @@ static const struct irq_domain_ops tegra_pmc_irq_domain_ops = {\n \t.alloc = tegra_pmc_irq_alloc,\n };\n \n+static int tegra210_pmc_irq_set_wake(struct irq_data *data, unsigned int on)\n+{\n+\tstruct tegra_pmc *pmc = irq_data_get_irq_chip_data(data);\n+\tunsigned int offset, bit;\n+\tu32 value;\n+\n+\tif (data->hwirq == ULONG_MAX)\n+\t\treturn 0;\n+\n+\toffset = data->hwirq / 32;\n+\tbit = data->hwirq % 32;\n+\n+\t/*\n+\t * latch wakeups to SW_WAKE_STATUS register to capture events\n+\t * that would not make it into wakeup event register during LP0 exit.\n+\t */\n+\tvalue = tegra_pmc_readl(pmc, PMC_CNTRL);\n+\tvalue |= PMC_CNTRL_LATCH_WAKEUPS;\n+\ttegra_pmc_writel(pmc, value, PMC_CNTRL);\n+\tudelay(120);\n+\n+\tvalue &= ~PMC_CNTRL_LATCH_WAKEUPS;\n+\ttegra_pmc_writel(pmc, value, PMC_CNTRL);\n+\tudelay(120);\n+\n+\ttegra_pmc_writel(pmc, 0, PMC_SW_WAKE_STATUS);\n+\ttegra_pmc_writel(pmc, 0, PMC_SW_WAKE2_STATUS);\n+\n+\ttegra_pmc_writel(pmc, 0, PMC_WAKE_STATUS);\n+\ttegra_pmc_writel(pmc, 0, PMC_WAKE2_STATUS);\n+\n+\t/* enable PMC wake */\n+\tif (data->hwirq >= 32)\n+\t\toffset = PMC_WAKE2_MASK;\n+\telse\n+\t\toffset = PMC_WAKE_MASK;\n+\n+\tvalue = tegra_pmc_readl(pmc, offset);\n+\n+\tif (on)\n+\t\tvalue |= 1 << bit;\n+\telse\n+\t\tvalue &= ~(1 << bit);\n+\n+\ttegra_pmc_writel(pmc, value, offset);\n+\n+\treturn 0;\n+}\n+\n static int tegra186_pmc_irq_set_wake(struct irq_data *data, unsigned int on)\n {\n \tstruct tegra_pmc *pmc = irq_data_get_irq_chip_data(data);\n@@ -1953,6 +2013,49 @@ static int tegra186_pmc_irq_set_wake(struct irq_data *data, unsigned int on)\n \treturn 0;\n }\n \n+static int tegra210_pmc_irq_set_type(struct irq_data *data, unsigned int type)\n+{\n+\tstruct tegra_pmc *pmc = irq_data_get_irq_chip_data(data);\n+\tunsigned int offset, bit;\n+\tu32 value;\n+\n+\tif (data->hwirq == ULONG_MAX)\n+\t\treturn 0;\n+\n+\toffset = data->hwirq / 32;\n+\tbit = data->hwirq % 32;\n+\n+\tif (data->hwirq >= 32)\n+\t\toffset = PMC_WAKE2_LEVEL;\n+\telse\n+\t\toffset = PMC_WAKE_LEVEL;\n+\n+\tvalue = tegra_pmc_readl(pmc, offset);\n+\n+\tswitch (type) {\n+\tcase IRQ_TYPE_EDGE_RISING:\n+\tcase IRQ_TYPE_LEVEL_HIGH:\n+\t\tvalue |= 1 << bit;\n+\t\tbreak;\n+\n+\tcase IRQ_TYPE_EDGE_FALLING:\n+\tcase IRQ_TYPE_LEVEL_LOW:\n+\t\tvalue &= ~(1 << bit);\n+\t\tbreak;\n+\n+\tcase IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING:\n+\t\tvalue ^= 1 << bit;\n+\t\tbreak;\n+\n+\tdefault:\n+\t\treturn -EINVAL;\n+\t}\n+\n+\ttegra_pmc_writel(pmc, value, offset);\n+\n+\treturn 0;\n+}\n+\n static int tegra186_pmc_irq_set_type(struct irq_data *data, unsigned int type)\n {\n \tstruct tegra_pmc *pmc = irq_data_get_irq_chip_data(data);\n@@ -2541,6 +2644,10 @@ static const struct pinctrl_pin_desc tegra210_pin_descs[] = {\n \tTEGRA210_IO_PAD_TABLE(TEGRA_IO_PIN_DESC)\n };\n \n+static const struct tegra_wake_event tegra210_wake_events[] = {\n+\tTEGRA_WAKE_IRQ(\"rtc\", 16, 2),\n+};\n+\n static const struct tegra_pmc_soc tegra210_pmc_soc = {\n \t.num_powergates = ARRAY_SIZE(tegra210_powergates),\n \t.powergates = tegra210_powergates,\n@@ -2558,10 +2665,14 @@ static const struct tegra_pmc_soc tegra210_pmc_soc = {\n \t.regs = &tegra20_pmc_regs,\n \t.init = tegra20_pmc_init,\n \t.setup_irq_polarity = tegra20_pmc_setup_irq_polarity,\n+\t.irq_set_wake = tegra210_pmc_irq_set_wake,\n+\t.irq_set_type = tegra210_pmc_irq_set_type,\n \t.reset_sources = tegra210_reset_sources,\n \t.num_reset_sources = ARRAY_SIZE(tegra210_reset_sources),\n \t.reset_levels = NULL,\n \t.num_reset_levels = 0,\n+\t.num_wake_events = ARRAY_SIZE(tegra210_wake_events),\n+\t.wake_events = tegra210_wake_events,\n };\n \n #define TEGRA186_IO_PAD_TABLE(_pad)\t\t\t\t\t \\\n","prefixes":["V3","13/17"]}