{"id":1117684,"url":"http://patchwork.ozlabs.org/api/patches/1117684/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-gpio/patch/1560843991-24123-15-git-send-email-skomatineni@nvidia.com/","project":{"id":42,"url":"http://patchwork.ozlabs.org/api/projects/42/?format=json","name":"Linux GPIO development","link_name":"linux-gpio","list_id":"linux-gpio.vger.kernel.org","list_email":"linux-gpio@vger.kernel.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<1560843991-24123-15-git-send-email-skomatineni@nvidia.com>","list_archive_url":null,"date":"2019-06-18T07:46:28","name":"[V3,14/17] arm64: tegra: enable wake from deep sleep on RTC alarm.","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"140c986e310bbe1014c362352e510fd1103b17e5","submitter":{"id":75554,"url":"http://patchwork.ozlabs.org/api/people/75554/?format=json","name":"Sowjanya Komatineni","email":"skomatineni@nvidia.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/linux-gpio/patch/1560843991-24123-15-git-send-email-skomatineni@nvidia.com/mbox/","series":[{"id":114436,"url":"http://patchwork.ozlabs.org/api/series/114436/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-gpio/list/?series=114436","date":"2019-06-18T07:46:16","name":"SC7 entry and exit support for Tegra210","version":3,"mbox":"http://patchwork.ozlabs.org/series/114436/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/1117684/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/1117684/checks/","tags":{},"related":[],"headers":{"Return-Path":"<linux-gpio-owner@vger.kernel.org>","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=linux-gpio-owner@vger.kernel.org;\n\treceiver=<UNKNOWN>)","ozlabs.org;\n\tdmarc=pass (p=none dis=none) header.from=nvidia.com","ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=nvidia.com header.i=@nvidia.com\n\theader.b=\"DiM1ZPkH\"; dkim-atps=neutral"],"Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 45SgCn6Kyxz9s00\n\tfor <incoming@patchwork.ozlabs.org>;\n\tTue, 18 Jun 2019 17:47:33 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1729199AbfFRHrO (ORCPT <rfc822;incoming@patchwork.ozlabs.org>);\n\tTue, 18 Jun 2019 03:47:14 -0400","from hqemgate16.nvidia.com ([216.228.121.65]:14184 \"EHLO\n\thqemgate16.nvidia.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1726238AbfFRHrN (ORCPT\n\t<rfc822; linux-gpio@vger.kernel.org>); Tue, 18 Jun 2019 03:47:13 -0400","from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by\n\thqemgate16.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA)\n\tid <B5d0897000000>; Tue, 18 Jun 2019 00:47:12 -0700","from hqmail.nvidia.com ([172.20.161.6])\n\tby hqpgpgate102.nvidia.com (PGP Universal service);\n\tTue, 18 Jun 2019 00:47:12 -0700","from HQMAIL106.nvidia.com (172.18.146.12) by HQMAIL107.nvidia.com\n\t(172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3;\n\tTue, 18 Jun 2019 07:47:12 +0000","from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL106.nvidia.com\n\t(172.18.146.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via\n\tFrontend Transport; Tue, 18 Jun 2019 07:47:12 +0000","from skomatineni-linux.nvidia.com (Not Verified[10.2.168.217]) by\n\thqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121)\n\tid <B5d0896fd0008>; Tue, 18 Jun 2019 00:47:12 -0700"],"X-PGP-Universal":"processed;\n\tby hqpgpgate102.nvidia.com on Tue, 18 Jun 2019 00:47:12 -0700","From":"Sowjanya Komatineni <skomatineni@nvidia.com>","To":"<thierry.reding@gmail.com>, <jonathanh@nvidia.com>,\n\t<tglx@linutronix.de>, <jason@lakedaemon.net>,\n\t<marc.zyngier@arm.com>, <linus.walleij@linaro.org>,\n\t<stefan@agner.ch>, <mark.rutland@arm.com>","CC":"<pdeschrijver@nvidia.com>, <pgaikwad@nvidia.com>,\n\t<sboyd@kernel.org>, <linux-clk@vger.kernel.org>,\n\t<linux-gpio@vger.kernel.org>, <jckuo@nvidia.com>,\n\t<josephl@nvidia.com>, <talho@nvidia.com>, <skomatineni@nvidia.com>,\n\t<linux-tegra@vger.kernel.org>, <linux-kernel@vger.kernel.org>,\n\t<mperttunen@nvidia.com>, <spatra@nvidia.com>, <robh+dt@kernel.org>,\n\t<digetx@gmail.com>, <devicetree@vger.kernel.org>","Subject":"[PATCH V3 14/17] arm64: tegra: enable wake from deep sleep on RTC\n\talarm.","Date":"Tue, 18 Jun 2019 00:46:28 -0700","Message-ID":"<1560843991-24123-15-git-send-email-skomatineni@nvidia.com>","X-Mailer":"git-send-email 2.7.4","In-Reply-To":"<1560843991-24123-1-git-send-email-skomatineni@nvidia.com>","References":"<1560843991-24123-1-git-send-email-skomatineni@nvidia.com>","X-NVConfidentiality":"public","MIME-Version":"1.0","Content-Type":"text/plain","DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1;\n\tt=1560844032; bh=yDxMxfPTCgsxiYAL44L3iSaV2tcgK1454UaiFZ8F9DY=;\n\th=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer:\n\tIn-Reply-To:References:X-NVConfidentiality:MIME-Version:\n\tContent-Type;\n\tb=DiM1ZPkHoJ3e4hCEshegM+ypO5Nk6Dg+7HkEwkEqAHgpFP9jPBYMzMQOilOP/K1ov\n\tX8UlnOJeWLoDr4sriHXCFNdJn/1pyP7ALUK9+qbklirmCiwgGBahjstHa4okk65dC3\n\trKc+yWPHnwTD3m01H9CjFenyQpl3MdiLt9Y823YvQqknkZRU5Nt3KE48DfwdsEQiJT\n\tEkPeBXAFzI4iX1g1t+3rUl6CkuNR5HAscbtr/B6Sbtkq8/y104qW3J942jCow7NtUb\n\tfpv1M7y0+pTo+SfudFOwS3/ixI3XZYEtUHjkuAMBgpmysMzqS+koukOFctJoaQjy+8\n\tuUpWa0yKwlNsw==","Sender":"linux-gpio-owner@vger.kernel.org","Precedence":"bulk","List-ID":"<linux-gpio.vger.kernel.org>","X-Mailing-List":"linux-gpio@vger.kernel.org"},"content":"This patch updates device tree for RTC and PMC to allow system wake\nfrom deep sleep on RTC alarm.\n\nSigned-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>\n---\n arch/arm64/boot/dts/nvidia/tegra210.dtsi | 5 ++++-\n 1 file changed, 4 insertions(+), 1 deletion(-)","diff":"diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi\nindex edf27fe2f10e..d284bd6088af 100644\n--- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi\n+++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi\n@@ -763,7 +763,8 @@\n \trtc@7000e000 {\n \t\tcompatible = \"nvidia,tegra210-rtc\", \"nvidia,tegra20-rtc\";\n \t\treg = <0x0 0x7000e000 0x0 0x100>;\n-\t\tinterrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;\n+\t\tinterrupts = <16 IRQ_TYPE_LEVEL_HIGH>;\n+\t\tinterrupt-parent = <&pmc>;\n \t\tclocks = <&tegra_car TEGRA210_CLK_RTC>;\n \t\tclock-names = \"rtc\";\n \t};\n@@ -773,6 +774,8 @@\n \t\treg = <0x0 0x7000e400 0x0 0x400>;\n \t\tclocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>;\n \t\tclock-names = \"pclk\", \"clk32k_in\";\n+\t\t#interrupt-cells = <2>;\n+\t\tinterrupt-controller;\n \n \t\tpowergates {\n \t\t\tpd_audio: aud {\n","prefixes":["V3","14/17"]}