{"id":1019106,"url":"http://patchwork.ozlabs.org/api/patches/1019106/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/1545989148-13582-9-git-send-email-aleksandar.markovic@rt-rk.com/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<1545989148-13582-9-git-send-email-aleksandar.markovic@rt-rk.com>","list_archive_url":null,"date":"2018-12-28T09:25:15","name":"[PULL,08/41] target/mips: MXU: Improve the comment containing MXU overview","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"822dfa705f90931091d636c89846e4d0b5331ff9","submitter":{"id":68635,"url":"http://patchwork.ozlabs.org/api/people/68635/?format=json","name":"Aleksandar Markovic","email":"aleksandar.markovic@rt-rk.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/1545989148-13582-9-git-send-email-aleksandar.markovic@rt-rk.com/mbox/","series":[{"id":83742,"url":"http://patchwork.ozlabs.org/api/series/83742/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=83742","date":"2018-12-28T09:25:09","name":"[PULL,01/41] MAINTAINERS: target/mips: Add MIPS files under default-configs directory","version":1,"mbox":"http://patchwork.ozlabs.org/series/83742/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/1019106/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/1019106/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=208.118.235.17; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=)","ozlabs.org;\n\tdmarc=none (p=none dis=none) header.from=rt-rk.com"],"Received":["from lists.gnu.org (lists.gnu.org [208.118.235.17])\n\t(using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 43R1fG3bH6z9s55\n\tfor ;\n\tFri, 28 Dec 2018 20:30:46 +1100 (AEDT)","from localhost ([127.0.0.1]:57767 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t)\n\tid 1gcoTc-0005CZ-7E\n\tfor incoming@patchwork.ozlabs.org; Fri, 28 Dec 2018 04:30:44 -0500","from eggs.gnu.org ([208.118.235.92]:48006)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from ) id 1gcoPH-0000pW-Bq\n\tfor qemu-devel@nongnu.org; Fri, 28 Dec 2018 04:26:42 -0500","from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from ) id 1gcoPB-0003Hj-Gl\n\tfor qemu-devel@nongnu.org; Fri, 28 Dec 2018 04:26:15 -0500","from mx2.rt-rk.com ([89.216.37.149]:49210 helo=mail.rt-rk.com)\n\tby eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32)\n\t(Exim 4.71) (envelope-from )\n\tid 1gcoPB-00034j-2K\n\tfor qemu-devel@nongnu.org; Fri, 28 Dec 2018 04:26:09 -0500","from localhost (localhost [127.0.0.1])\n\tby mail.rt-rk.com (Postfix) with ESMTP id 0F3621A210F;\n\tFri, 28 Dec 2018 10:25:55 +0100 (CET)","from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local\n\t[10.10.13.43])\n\tby mail.rt-rk.com (Postfix) with ESMTPSA id C1B1C1A211E;\n\tFri, 28 Dec 2018 10:25:54 +0100 (CET)"],"X-Virus-Scanned":"amavisd-new at rt-rk.com","From":"Aleksandar Markovic ","To":"qemu-devel@nongnu.org","Date":"Fri, 28 Dec 2018 10:25:15 +0100","Message-Id":"<1545989148-13582-9-git-send-email-aleksandar.markovic@rt-rk.com>","X-Mailer":"git-send-email 2.7.4","In-Reply-To":"<1545989148-13582-1-git-send-email-aleksandar.markovic@rt-rk.com>","References":"<1545989148-13582-1-git-send-email-aleksandar.markovic@rt-rk.com>","MIME-Version":"1.0","Content-Type":"text/plain; charset=UTF-8","Content-Transfer-Encoding":"quoted-printable","X-detected-operating-system":"by eggs.gnu.org: GNU/Linux 3.x [fuzzy]","X-Received-From":"89.216.37.149","Subject":"[Qemu-devel] [PULL 08/41] target/mips: MXU: Improve the comment\n\tcontaining MXU overview","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"peter.maydell@linaro.org, amarkovic@wavecomp.com","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"\"Qemu-devel\"\n\t"},"content":"From: Aleksandar Markovic \n\nImprove textual description of MXU extension. These are mostly\ncomment formatting changes.\n\nReviewed-by: Stefan Markovic \nSigned-off-by: Aleksandar Markovic \n---\n target/mips/translate.c | 74 +++++++++++++++++++++++++++++--------------------\n 1 file changed, 44 insertions(+), 30 deletions(-)","diff":"diff --git a/target/mips/translate.c b/target/mips/translate.c\nindex 74d16ce..e3a5a73 100644\n--- a/target/mips/translate.c\n+++ b/target/mips/translate.c\n@@ -1399,10 +1399,12 @@ enum {\n \n \n /*\n- * AN OVERVIEW OF MXU EXTENSION INSTRUCTION SET\n- * ============================================\n *\n- * MXU (full name: MIPS eXtension/enhanced Unit) is an SIMD extension of MIPS32\n+ * AN OVERVIEW OF MXU EXTENSION INSTRUCTION SET\n+ * ============================================\n+ *\n+ *\n+ * MXU (full name: MIPS eXtension/enhanced Unit) is a SIMD extension of MIPS32\n * instructions set. It is designed to fit the needs of signal, graphical and\n * video processing applications. MXU instruction set is used in Xburst family\n * of microprocessors by Ingenic.\n@@ -1410,39 +1412,31 @@ enum {\n * MXU unit contains 17 registers called X0-X16. X0 is always zero, and X16 is\n * the control register.\n *\n- * The notation used in MXU assembler mnemonics\n- * --------------------------------------------\n *\n- * Registers:\n+ * The notation used in MXU assembler mnemonics\n+ * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n+ *\n+ * Register operands:\n *\n * XRa, XRb, XRc, XRd - MXU registers\n * Rb, Rc, Rd, Rs, Rt - general purpose MIPS registers\n *\n- * Subfields:\n+ * Non-register operands:\n *\n- * aptn1 - 1-bit accumulate add/subtract pattern\n- * aptn2 - 2-bit accumulate add/subtract pattern\n- * eptn2 - 2-bit execute add/subtract pattern\n- * optn2 - 2-bit operand pattern\n- * optn3 - 3-bit operand pattern\n- * sft4 - 4-bit shift amount\n- * strd2 - 2-bit stride amount\n+ * aptn1 - 1-bit accumulate add/subtract pattern\n+ * aptn2 - 2-bit accumulate add/subtract pattern\n+ * eptn2 - 2-bit execute add/subtract pattern\n+ * optn2 - 2-bit operand pattern\n+ * optn3 - 3-bit operand pattern\n+ * sft4 - 4-bit shift amount\n+ * strd2 - 2-bit stride amount\n *\n * Prefixes:\n *\n- * \n- * S 32\n- * D 16\n- * Q 8\n- *\n- * Suffixes:\n- *\n- * E - Expand results\n- * F - Fixed point multiplication\n- * L - Low part result\n- * R - Doing rounding\n- * V - Variable instead of immediate\n- * W - Combine above L and V\n+ * Level of parallelism: Operand size:\n+ * S - single operation at a time 32 - word\n+ * D - two operations in parallel 16 - half word\n+ * Q - four operations in parallel 8 - byte\n *\n * Operations:\n *\n@@ -1486,6 +1480,19 @@ enum {\n * SCOP - Calculate x’s scope (-1, means x<0; 0, means x==0; 1, means x>0)\n * XOR - Logical bitwise 'exclusive or' operation\n *\n+ * Suffixes:\n+ *\n+ * E - Expand results\n+ * F - Fixed point multiplication\n+ * L - Low part result\n+ * R - Doing rounding\n+ * V - Variable instead of immediate\n+ * W - Combine above L and V\n+ *\n+ *\n+ * The list of MXU instructions grouped by functionality\n+ * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n+ *\n * Load/Store instructions Multiplication instructions\n * ----------------------- ---------------------------\n *\n@@ -1563,6 +1570,13 @@ enum {\n * Q16SAT XRa, XRb, XRc S32I2M XRa, Rb\n *\n *\n+ * The opcode organization of MXU instructions\n+ * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n+ *\n+ * The bits 31..26 of all MXU instructions are equal to 0x1C (also referred\n+ * as opcode SPECIAL2 in the base MIPS ISA). The organization and meaning of\n+ * other bits up to the instruction level is as follows:\n+ *\n * bits\n * 05..00\n *\n@@ -1700,7 +1714,7 @@ enum {\n * │ ├─ 010 ─ OPC_MXU_D16MOVZ\n * │ ├─ 011 ─ OPC_MXU_D16MOVN\n * │ ├─ 100 ─ OPC_MXU_S32MOVZ\n- * │ └─ 101 ─ OPC_MXU_S32MOV\n+ * │ └─ 101 ─ OPC_MXU_S32MOVN\n * │\n * │ 23..22\n * ├─ 111010 ─ OPC_MXU__POOL21 ─┬─ 00 ─ OPC_MXU_Q8MAC\n@@ -1712,10 +1726,10 @@ enum {\n * └─ 111111 ─ (overlaps with SDBBP)\n *\n *\n- * Compiled after:\n+ * Compiled after:\n *\n * \"XBurst® Instruction Set Architecture MIPS eXtension/enhanced Unit\n- * Programming Manual\", Ingenic Semiconductor Co, Ltd., 2017\n+ * Programming Manual\", Ingenic Semiconductor Co, Ltd., revision June 2, 2017\n */\n \n enum {\n","prefixes":["PULL","08/41"]}