{"id":1019105,"url":"http://patchwork.ozlabs.org/api/patches/1019105/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/1545989148-13582-10-git-send-email-aleksandar.markovic@rt-rk.com/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<1545989148-13582-10-git-send-email-aleksandar.markovic@rt-rk.com>","list_archive_url":null,"date":"2018-12-28T09:25:16","name":"[PULL,09/41] target/mips: Support R5900 three-operand MADD and MADDU instructions","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"59a02f6d0c8d9173577d77372e6a72089105164c","submitter":{"id":68635,"url":"http://patchwork.ozlabs.org/api/people/68635/?format=json","name":"Aleksandar Markovic","email":"aleksandar.markovic@rt-rk.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/1545989148-13582-10-git-send-email-aleksandar.markovic@rt-rk.com/mbox/","series":[{"id":83742,"url":"http://patchwork.ozlabs.org/api/series/83742/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=83742","date":"2018-12-28T09:25:09","name":"[PULL,01/41] MAINTAINERS: target/mips: Add MIPS files under default-configs directory","version":1,"mbox":"http://patchwork.ozlabs.org/series/83742/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/1019105/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/1019105/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=208.118.235.17; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=)","ozlabs.org;\n\tdmarc=none (p=none dis=none) header.from=rt-rk.com"],"Received":["from lists.gnu.org (lists.gnu.org [208.118.235.17])\n\t(using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 43R1f13ddyz9s2P\n\tfor ;\n\tFri, 28 Dec 2018 20:30:33 +1100 (AEDT)","from localhost ([127.0.0.1]:57762 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t)\n\tid 1gcoTP-0004oM-7o\n\tfor incoming@patchwork.ozlabs.org; Fri, 28 Dec 2018 04:30:31 -0500","from eggs.gnu.org ([208.118.235.92]:47765)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from ) id 1gcoP3-0000X9-Q4\n\tfor qemu-devel@nongnu.org; Fri, 28 Dec 2018 04:26:04 -0500","from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from ) id 1gcoP1-00036K-Bh\n\tfor qemu-devel@nongnu.org; Fri, 28 Dec 2018 04:26:01 -0500","from mx2.rt-rk.com ([89.216.37.149]:49206 helo=mail.rt-rk.com)\n\tby eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32)\n\t(Exim 4.71) (envelope-from )\n\tid 1gcoP0-00034d-U1\n\tfor qemu-devel@nongnu.org; Fri, 28 Dec 2018 04:25:59 -0500","from localhost (localhost [127.0.0.1])\n\tby mail.rt-rk.com (Postfix) with ESMTP id 1CB4C1A213C;\n\tFri, 28 Dec 2018 10:25:55 +0100 (CET)","from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local\n\t[10.10.13.43])\n\tby mail.rt-rk.com (Postfix) with ESMTPSA id C9EF71A20BE;\n\tFri, 28 Dec 2018 10:25:54 +0100 (CET)"],"X-Virus-Scanned":"amavisd-new at rt-rk.com","From":"Aleksandar Markovic ","To":"qemu-devel@nongnu.org","Date":"Fri, 28 Dec 2018 10:25:16 +0100","Message-Id":"<1545989148-13582-10-git-send-email-aleksandar.markovic@rt-rk.com>","X-Mailer":"git-send-email 2.7.4","In-Reply-To":"<1545989148-13582-1-git-send-email-aleksandar.markovic@rt-rk.com>","References":"<1545989148-13582-1-git-send-email-aleksandar.markovic@rt-rk.com>","MIME-Version":"1.0","Content-Type":"text/plain; charset=UTF-8","Content-Transfer-Encoding":"quoted-printable","X-detected-operating-system":"by eggs.gnu.org: GNU/Linux 3.x [fuzzy]","X-Received-From":"89.216.37.149","Subject":"[Qemu-devel] [PULL 09/41] target/mips: Support R5900 three-operand\n\tMADD and MADDU instructions","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"peter.maydell@linaro.org, amarkovic@wavecomp.com","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"\"Qemu-devel\"\n\t"},"content":"From: Philippe Mathieu-Daudé \n\nThe three-operand MADD and MADDU are specific to Sony R5900 core,\nand Toshiba TX19/TX39/TX79 cores as well.\n\nThe \"32-Bit TX System RISC TX39 Family Architecture manual\"\nis available at https://wiki.qemu.org/File:DSAE0022432.pdf\n\nReviewed-by: Aleksandar Markovic \nSigned-off-by: Aleksandar Markovic \nSigned-off-by: Philippe Mathieu-Daudé\nSigned-off-by: Fredrik Noring \nTested-by: Fredrik Noring \n---\n target/mips/translate.c | 58 ++++++++++++++++++++++++++++++++++++++++++++-----\n 1 file changed, 53 insertions(+), 5 deletions(-)","diff":"diff --git a/target/mips/translate.c b/target/mips/translate.c\nindex e3a5a73..3ad3b31 100644\n--- a/target/mips/translate.c\n+++ b/target/mips/translate.c\n@@ -5027,8 +5027,8 @@ static void gen_muldiv(DisasContext *ctx, uint32_t opc,\n }\n \n /*\n- * These MULT and MULTU instructions implemented in for example the\n- * Toshiba/Sony R5900 and the Toshiba TX19, TX39 and TX79 core\n+ * These MULT[U] and MADD[U] instructions implemented in for example\n+ * the Toshiba/Sony R5900 and the Toshiba TX19, TX39 and TX79 core\n * architectures are special three-operand variants with the syntax\n *\n * MULT[U][1] rd, rs, rt\n@@ -5037,6 +5037,14 @@ static void gen_muldiv(DisasContext *ctx, uint32_t opc,\n *\n * (rd, LO, HI) <- rs * rt\n *\n+ * and\n+ *\n+ * MADD[U] rd, rs, rt\n+ *\n+ * such that\n+ *\n+ * (rd, LO, HI) <- (LO, HI) + rs * rt\n+ *\n * where the low-order 32-bits of the result is placed into both the\n * GPR rd and the special register LO. The high-order 32-bits of the\n * result is placed into the special register HI.\n@@ -5093,8 +5101,48 @@ static void gen_mul_txx9(DisasContext *ctx, uint32_t opc,\n tcg_temp_free_i32(t3);\n }\n break;\n+ case MMI_OPC_MADD:\n+ {\n+ TCGv_i64 t2 = tcg_temp_new_i64();\n+ TCGv_i64 t3 = tcg_temp_new_i64();\n+\n+ tcg_gen_ext_tl_i64(t2, t0);\n+ tcg_gen_ext_tl_i64(t3, t1);\n+ tcg_gen_mul_i64(t2, t2, t3);\n+ tcg_gen_concat_tl_i64(t3, cpu_LO[acc], cpu_HI[acc]);\n+ tcg_gen_add_i64(t2, t2, t3);\n+ tcg_temp_free_i64(t3);\n+ gen_move_low32(cpu_LO[acc], t2);\n+ gen_move_high32(cpu_HI[acc], t2);\n+ if (rd) {\n+ gen_move_low32(cpu_gpr[rd], t2);\n+ }\n+ tcg_temp_free_i64(t2);\n+ }\n+ break;\n+ case MMI_OPC_MADDU:\n+ {\n+ TCGv_i64 t2 = tcg_temp_new_i64();\n+ TCGv_i64 t3 = tcg_temp_new_i64();\n+\n+ tcg_gen_ext32u_tl(t0, t0);\n+ tcg_gen_ext32u_tl(t1, t1);\n+ tcg_gen_extu_tl_i64(t2, t0);\n+ tcg_gen_extu_tl_i64(t3, t1);\n+ tcg_gen_mul_i64(t2, t2, t3);\n+ tcg_gen_concat_tl_i64(t3, cpu_LO[acc], cpu_HI[acc]);\n+ tcg_gen_add_i64(t2, t2, t3);\n+ tcg_temp_free_i64(t3);\n+ gen_move_low32(cpu_LO[acc], t2);\n+ gen_move_high32(cpu_HI[acc], t2);\n+ if (rd) {\n+ gen_move_low32(cpu_gpr[rd], t2);\n+ }\n+ tcg_temp_free_i64(t2);\n+ }\n+ break;\n default:\n- MIPS_INVAL(\"mul TXx9\");\n+ MIPS_INVAL(\"mul/madd TXx9\");\n generate_exception_end(ctx, EXCP_RI);\n goto out;\n }\n@@ -26703,6 +26751,8 @@ static void decode_mmi(CPUMIPSState *env, DisasContext *ctx)\n break;\n case MMI_OPC_MULT1:\n case MMI_OPC_MULTU1:\n+ case MMI_OPC_MADD:\n+ case MMI_OPC_MADDU:\n gen_mul_txx9(ctx, opc, rd, rs, rt);\n break;\n case MMI_OPC_DIV1:\n@@ -26717,8 +26767,6 @@ static void decode_mmi(CPUMIPSState *env, DisasContext *ctx)\n case MMI_OPC_MFHI1:\n gen_HILO1_tx79(ctx, opc, rd);\n break;\n- case MMI_OPC_MADD: /* TODO: MMI_OPC_MADD */\n- case MMI_OPC_MADDU: /* TODO: MMI_OPC_MADDU */\n case MMI_OPC_PLZCW: /* TODO: MMI_OPC_PLZCW */\n case MMI_OPC_MADD1: /* TODO: MMI_OPC_MADD1 */\n case MMI_OPC_MADDU1: /* TODO: MMI_OPC_MADDU1 */\n","prefixes":["PULL","09/41"]}