{"id":1019104,"url":"http://patchwork.ozlabs.org/api/patches/1019104/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/1545989148-13582-6-git-send-email-aleksandar.markovic@rt-rk.com/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<1545989148-13582-6-git-send-email-aleksandar.markovic@rt-rk.com>","list_archive_url":null,"date":"2018-12-28T09:25:12","name":"[PULL,05/41] atomics: Set ATOMIC_REG_SIZE=8 for MIPS n32","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"59f361ad1779ffd211bbfa9b6f895cf40bf5534f","submitter":{"id":68635,"url":"http://patchwork.ozlabs.org/api/people/68635/?format=json","name":"Aleksandar Markovic","email":"aleksandar.markovic@rt-rk.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/1545989148-13582-6-git-send-email-aleksandar.markovic@rt-rk.com/mbox/","series":[{"id":83742,"url":"http://patchwork.ozlabs.org/api/series/83742/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=83742","date":"2018-12-28T09:25:09","name":"[PULL,01/41] MAINTAINERS: target/mips: Add MIPS files under default-configs directory","version":1,"mbox":"http://patchwork.ozlabs.org/series/83742/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/1019104/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/1019104/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=208.118.235.17; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=)","ozlabs.org;\n\tdmarc=none (p=none dis=none) header.from=rt-rk.com"],"Received":["from lists.gnu.org (lists.gnu.org [208.118.235.17])\n\t(using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 43R1dS2wXcz9s2P\n\tfor ;\n\tFri, 28 Dec 2018 20:30:04 +1100 (AEDT)","from localhost ([127.0.0.1]:57758 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t)\n\tid 1gcoSw-0004DN-6d\n\tfor incoming@patchwork.ozlabs.org; Fri, 28 Dec 2018 04:30:02 -0500","from eggs.gnu.org ([208.118.235.92]:47758)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from ) id 1gcoP3-0000WM-5l\n\tfor qemu-devel@nongnu.org; Fri, 28 Dec 2018 04:26:03 -0500","from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from ) id 1gcoP1-000367-8x\n\tfor qemu-devel@nongnu.org; Fri, 28 Dec 2018 04:26:01 -0500","from mx2.rt-rk.com ([89.216.37.149]:49195 helo=mail.rt-rk.com)\n\tby eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32)\n\t(Exim 4.71) (envelope-from )\n\tid 1gcoP0-00034Q-Um\n\tfor qemu-devel@nongnu.org; Fri, 28 Dec 2018 04:25:59 -0500","from localhost (localhost [127.0.0.1])\n\tby mail.rt-rk.com (Postfix) with ESMTP id DB0BB1A205E;\n\tFri, 28 Dec 2018 10:25:54 +0100 (CET)","from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local\n\t[10.10.13.43])\n\tby mail.rt-rk.com (Postfix) with ESMTPSA id A98B71A20C6;\n\tFri, 28 Dec 2018 10:25:54 +0100 (CET)"],"X-Virus-Scanned":"amavisd-new at rt-rk.com","From":"Aleksandar Markovic ","To":"qemu-devel@nongnu.org","Date":"Fri, 28 Dec 2018 10:25:12 +0100","Message-Id":"<1545989148-13582-6-git-send-email-aleksandar.markovic@rt-rk.com>","X-Mailer":"git-send-email 2.7.4","In-Reply-To":"<1545989148-13582-1-git-send-email-aleksandar.markovic@rt-rk.com>","References":"<1545989148-13582-1-git-send-email-aleksandar.markovic@rt-rk.com>","MIME-Version":"1.0","Content-Type":"text/plain; charset=UTF-8","Content-Transfer-Encoding":"quoted-printable","X-detected-operating-system":"by eggs.gnu.org: GNU/Linux 3.x [fuzzy]","X-Received-From":"89.216.37.149","Subject":"[Qemu-devel] [PULL 05/41] atomics: Set ATOMIC_REG_SIZE=8 for MIPS\n\tn32","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"peter.maydell@linaro.org, amarkovic@wavecomp.com","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"\"Qemu-devel\"\n\t"},"content":"From: Paul Burton \n\nATOMIC_REG_SIZE is currently defined as the default sizeof(void *) for\nall MIPS host builds, including those using the n32 ABI. n32 is the\nMIPS64 ILP32 ABI and as such tcg/mips/tcg-target.h defines\nTCG_TARGET_REG_BITS as 64 for n32 builds. If we attempt to build QEMU\nfor an n32 host with support for a 64b target architecture then\nTCG_OVERSIZED_GUEST is 0 and accel/tcg/cputlb.c attempts to use\natomic_* functions. This fails because ATOMIC_REG_SIZE is 4, causing\nthe calls to QEMU_BUILD_BUG_ON(sizeof(*ptr) > ATOMIC_REG_SIZE) in the\nvarious atomic_* functions to generate errors.\n\nFix this by defining ATOMIC_REG_SIZE as 8 for all MIPS64 builds, which\nwill cover both n32 (ILP32) & n64 (LP64) ABIs in much the same was as\nwe already do for x86_64/x32.\n\nReviewed-by: Philippe Mathieu-Daudé \nReviewed-by: Richard Henderson \nSigned-off-by: Aleksandar Markovic \nSigned-off-by: Paul Burton \n---\n include/qemu/atomic.h | 5 +++--\n 1 file changed, 3 insertions(+), 2 deletions(-)","diff":"diff --git a/include/qemu/atomic.h b/include/qemu/atomic.h\nindex f6993a8..a6ac188 100644\n--- a/include/qemu/atomic.h\n+++ b/include/qemu/atomic.h\n@@ -99,9 +99,10 @@\n * those few cases by hand.\n *\n * Note that x32 is fully detected with __x86_64__ + _ILP32, and that for\n- * Sparc we always force the use of sparcv9 in configure.\n+ * Sparc we always force the use of sparcv9 in configure. MIPS n32 (ILP32) &\n+ * n64 (LP64) ABIs are both detected using __mips64.\n */\n-#if defined(__x86_64__) || defined(__sparc__)\n+#if defined(__x86_64__) || defined(__sparc__) || defined(__mips64)\n # define ATOMIC_REG_SIZE 8\n #else\n # define ATOMIC_REG_SIZE sizeof(void *)\n","prefixes":["PULL","05/41"]}