{"id":819364,"url":"http://patchwork.ozlabs.org/api/covers/819364/?format=json","web_url":"http://patchwork.ozlabs.org/project/devicetree-bindings/cover/20170928005756.3938-1-kalyan.kinthada@alliedtelesis.co.nz/","project":{"id":37,"url":"http://patchwork.ozlabs.org/api/projects/37/?format=json","name":"Devicetree Bindings","link_name":"devicetree-bindings","list_id":"devicetree.vger.kernel.org","list_email":"devicetree@vger.kernel.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20170928005756.3938-1-kalyan.kinthada@alliedtelesis.co.nz>","list_archive_url":null,"date":"2017-09-28T00:57:55","name":"[v3,0/1] Set FORCE_CSX bit when arbitration between NAND and NOR is enabled.","submitter":{"id":72417,"url":"http://patchwork.ozlabs.org/api/people/72417/?format=json","name":"Kalyan Kinthada","email":"kalyan.kinthada@alliedtelesis.co.nz"},"mbox":"http://patchwork.ozlabs.org/project/devicetree-bindings/cover/20170928005756.3938-1-kalyan.kinthada@alliedtelesis.co.nz/mbox/","series":[{"id":5467,"url":"http://patchwork.ozlabs.org/api/series/5467/?format=json","web_url":"http://patchwork.ozlabs.org/project/devicetree-bindings/list/?series=5467","date":"2017-09-28T00:57:55","name":"Set FORCE_CSX bit when arbitration between NAND and NOR is enabled.","version":3,"mbox":"http://patchwork.ozlabs.org/series/5467/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/covers/819364/comments/","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=alliedtelesis.co.nz\n\theader.i=@alliedtelesis.co.nz\n\theader.b=\"XoqRmq8P\"; dkim-atps=neutral"],"Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3y2bs91dr3z9t5C\n\tfor ;\n\tThu, 28 Sep 2017 10:58:05 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1752540AbdI1A6D (ORCPT\n\t);\n\tWed, 27 Sep 2017 20:58:03 -0400","from gate2.alliedtelesis.co.nz ([202.36.163.20]:52266 \"EHLO\n\tgate2.alliedtelesis.co.nz\" rhost-flags-OK-OK-OK-OK) by\n\tvger.kernel.org with ESMTP id S1752534AbdI1A6D (ORCPT\n\t); Wed, 27 Sep 2017 20:58:03 -0400","from mmarshal3.atlnz.lc (mmarshal3.atlnz.lc [10.32.18.43])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (Client did not present a certificate)\n\tby gate2.alliedtelesis.co.nz (Postfix) with ESMTPS id A323E806A8;\n\tThu, 28 Sep 2017 13:58:00 +1300 (NZDT)","from smtp (Not Verified[10.32.16.33]) by mmarshal3.atlnz.lc with\n\tTrustwave SEG (v7, 5, 8, 10121)\n\tid ; Thu, 28 Sep 2017 13:58:00 +1300","from kalyank-dl.ws.atlnz.lc (kalyank-dl.ws.atlnz.lc [10.33.14.14])\n\tby smtp (Postfix) with ESMTP id C6D5413EEAD;\n\tThu, 28 Sep 2017 13:58:09 +1300 (NZDT)","by kalyank-dl.ws.atlnz.lc (Postfix, from userid 1628)\n\tid 480B8C0786; Thu, 28 Sep 2017 13:57:58 +1300 (NZDT)"],"DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed; d=alliedtelesis.co.nz; \n\ts=mail; t=1506560280;\n\tbh=nNB4aE53mN3CVs6sOtjXD2cTLrbGZLLC3sTzkFFOxbI=;\n\th=From:To:Cc:Subject:Date;\n\tb=XoqRmq8Pp4gHbIOa/Trv3vl6rf4A2lIhDxfWwhZ/+b+ZaswboP/X2kMUYzVhifpia\n\tlPuOArXUN4ttCsAF6MxgZrnA8w0AMTRexptLmU6+Ssy5xzrPyTDaIordo+Bqz6Kwfp\n\tyhyY2xEqyP8RobJVmcfgIQcyMjHEejU8oM7Q/wCQ=","From":"Kalyan Kinthada ","To":"dwmw2@infradead.org, computersforpeace@gmail.com,\n\tboris.brezillon@free-electrons.com, marek.vasut@gmail.com,\n\trichard@nod.at, cyrille.pitchen@wedev4u.fr, robh+dt@kernel.org,\n\tmark.rutland@arm.com, ezequiel.garcia@free-electrons.com,\n\tmiquel.raynal@free-electrons.com, devicetree@vger.kernel.org","Cc":"linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org,\n\tchris.packham@alliedtelesis.co.nz,\n\tKalyan Kinthada ","Subject":"[PATCH v3 0/1] Set FORCE_CSX bit when arbitration between NAND and\n\tNOR is enabled.","Date":"Thu, 28 Sep 2017 13:57:55 +1300","Message-Id":"<20170928005756.3938-1-kalyan.kinthada@alliedtelesis.co.nz>","X-Mailer":"git-send-email 2.14.1","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"},"content":"When the arbitration between NOR and NAND flash is enabled\nthe field bit[21] in the Data Flash Control Register\nneeds to be set to 1 according to guidleine GL-5830741\nmentioned in Marvell Errata document MV-S501377-00, Rev. D.\n\nSet the FORCE_CSX bit in NDCR for ARMADA370 variants as the arbitration\nis always enabled by default. This change does not apply for pxa3xx\nvariants because FORCE_CSX bit does not exist/reserved on the NFCv1.\n\nRan the \"flash_speed\" tool on NAND flash on a board with\nArmada-xp based SoC which uses only one NAND chip and not using\nthe arbiter. There is no regression or speed penalty\nintroduced due to this change.\n\nChanges since v2:\nThanks Miquel RAYNAL for the suggestion.\n\n* \"mtd: nand: pxa3xx: Set FORCE_CSX bit to ARMADA370 variants.\"\n Modified commit message to mention that this change does not apply\n for pxa3xx variants.\n Fixed the missing space in comments.\n Removed unused macros \"NDCR_ND_MODE\" and \"NDCR_NAND_MODE\".\n\nChanges since v1:\nThanks Miquel RAYNAL for the suggestion.\n\n* Deleted: \"dt-bindings: mtd: pxa3xx: Add \"marvell,nand-force-csx\" compatible string\"\n Not necessary to create a new compatible string.\n\n* \"mtd: nand: pxa3xx: Set FORCE_CSX bit to ARMADA370 variants.\"\n Modified commit message.\n This commit sets the FORCE_CSX bit for all ARMADA370 variants.\n\n-----\n\nKalyan Kinthada (1):\n mtd: nand: pxa3xx: Set FORCE_CSX bit to ARMADA370 variants.\n\n drivers/mtd/nand/pxa3xx_nand.c | 9 +++++++--\n 1 file changed, 7 insertions(+), 2 deletions(-)"}