{"id":819207,"url":"http://patchwork.ozlabs.org/api/covers/819207/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/cover/1506524205-20763-1-git-send-email-eric.auger@redhat.com/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<1506524205-20763-1-git-send-email-eric.auger@redhat.com>","list_archive_url":null,"date":"2017-09-27T14:56:42","name":"[RFC,0/3] vITS Reset","submitter":{"id":69187,"url":"http://patchwork.ozlabs.org/api/people/69187/?format=json","name":"Eric Auger","email":"eric.auger@redhat.com"},"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/cover/1506524205-20763-1-git-send-email-eric.auger@redhat.com/mbox/","series":[{"id":5384,"url":"http://patchwork.ozlabs.org/api/series/5384/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=5384","date":"2017-09-27T14:56:42","name":"vITS Reset","version":1,"mbox":"http://patchwork.ozlabs.org/series/5384/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/covers/819207/comments/","headers":{"Return-Path":"<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=<UNKNOWN>)","ext-mx04.extmail.prod.ext.phx2.redhat.com;\n\tdmarc=none (p=none dis=none) header.from=redhat.com","ext-mx04.extmail.prod.ext.phx2.redhat.com;\n\tspf=fail smtp.mailfrom=eric.auger@redhat.com"],"Received":["from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3y2LXj2Rs0z9tXw\n\tfor <incoming@patchwork.ozlabs.org>;\n\tThu, 28 Sep 2017 00:57:56 +1000 (AEST)","from localhost ([::1]:55149 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>)\n\tid 1dxDmb-0000at-3A\n\tfor incoming@patchwork.ozlabs.org; Wed, 27 Sep 2017 10:57:53 -0400","from eggs.gnu.org ([2001:4830:134:3::10]:56621)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from <eric.auger@redhat.com>) id 1dxDly-0000UC-7V\n\tfor qemu-devel@nongnu.org; Wed, 27 Sep 2017 10:57:15 -0400","from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from <eric.auger@redhat.com>) id 1dxDlu-0001Xl-HT\n\tfor qemu-devel@nongnu.org; Wed, 27 Sep 2017 10:57:14 -0400","from mx1.redhat.com ([209.132.183.28]:46290)\n\tby eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32)\n\t(Exim 4.71) (envelope-from <eric.auger@redhat.com>)\n\tid 1dxDll-0001Sw-Az; Wed, 27 Sep 2017 10:57:01 -0400","from smtp.corp.redhat.com\n\t(int-mx02.intmail.prod.int.phx2.redhat.com [10.5.11.12])\n\t(using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby mx1.redhat.com (Postfix) with ESMTPS id 264D121733;\n\tWed, 27 Sep 2017 14:57:00 +0000 (UTC)","from localhost.localdomain.com (ovpn-116-163.ams2.redhat.com\n\t[10.36.116.163])\n\tby smtp.corp.redhat.com (Postfix) with ESMTP id 7E0F894C6D;\n\tWed, 27 Sep 2017 14:56:53 +0000 (UTC)"],"DMARC-Filter":"OpenDMARC Filter v1.3.2 mx1.redhat.com 264D121733","From":"Eric Auger <eric.auger@redhat.com>","To":"eric.auger.pro@gmail.com, eric.auger@redhat.com, peter.maydell@linaro.org,\n\tqemu-arm@nongnu.org, qemu-devel@nongnu.org, wanghaibin.wang@huawei.com","Date":"Wed, 27 Sep 2017 16:56:42 +0200","Message-Id":"<1506524205-20763-1-git-send-email-eric.auger@redhat.com>","X-Scanned-By":"MIMEDefang 2.79 on 10.5.11.12","X-Greylist":"Sender IP whitelisted, not delayed by milter-greylist-4.5.16\n\t(mx1.redhat.com [10.5.110.28]);\n\tWed, 27 Sep 2017 14:57:00 +0000 (UTC)","X-detected-operating-system":"by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic]\n\t[fuzzy]","X-Received-From":"209.132.183.28","Subject":"[Qemu-devel] [RFC 0/3] vITS Reset","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"<qemu-devel.nongnu.org>","List-Unsubscribe":"<https://lists.nongnu.org/mailman/options/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>","List-Archive":"<http://lists.nongnu.org/archive/html/qemu-devel/>","List-Post":"<mailto:qemu-devel@nongnu.org>","List-Help":"<mailto:qemu-devel-request@nongnu.org?subject=help>","List-Subscribe":"<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=subscribe>","Cc":"wei@redhat.com, drjones@redhat.com, vijay.kilari@gmail.com,\n\tquintela@redhat.com, dgilbert@redhat.com, wu.wubin@huawei.com,\n\tchristoffer.dall@linaro.org","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"\"Qemu-devel\"\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>"},"content":"At the moment the ITS is not properly reset. On System reset or\nreboot, previous ITS register values and caches are left\nunchanged. Some of the registers might point to some guest RAM\ntables which are not provisionned. This leads to state\ninconsistencies that are detected by the kernel save/restore\ncode. And eventually this may cause qemu abort on source or\ndestination.\n\nThe 1st patch, suggested to be cc'ed stable proposes to remove\nthe abort in case of table save/restore failure. This is\ndefinitively not ideal but looks the most reasonable until we\nget a proper way to reset the ITS. Still a message is emitted\nto report the save/restore did not happen correctly.\n\nSubsequent patches add the support of explicit reset using\na new kvm device group/attribute combo. The associated kernel\nseries is not upstream [1], hence the RFC.\n\nITS specification is not very clear about reset. There is no\nreset wire. Some register fields are documented to have\narchitecturally defined reset values and we use those here:\nMost importantly the Valid bit of GITS_CBASER and GITS_BASER\nare cleared and the GITS_CTLR.Enabled bit is cleared as well.\n\nBest Regards\n\nEric\n\nHost Kernel dependencies:\n- [1] [PATCH 0/10 v2] vITS Migration fixes and reset\n\nThe series is available at:\nhttps://github.com/eauger/qemu/tree/v2.10-its-reset-v1\n\n\nEric Auger (3):\n  hw/intc/arm_gicv3_its: Don't abort on table save/restore\n  linux-headers: Partial header update for ITS reset\n  hw/intc/arm_gicv3_its: Implement reset\n\n hw/intc/arm_gicv3_its_common.c         |  5 ++---\n hw/intc/arm_gicv3_its_kvm.c            | 37 ++++++++++++++++++++++++----------\n include/hw/intc/arm_gicv3_its_common.h |  1 +\n linux-headers/asm-arm/kvm.h            |  1 +\n linux-headers/asm-arm64/kvm.h          |  1 +\n 5 files changed, 31 insertions(+), 14 deletions(-)"}