{"id":818877,"url":"http://patchwork.ozlabs.org/api/covers/818877/?format=json","web_url":"http://patchwork.ozlabs.org/project/devicetree-bindings/cover/20170927005516.28374-1-kalyan.kinthada@alliedtelesis.co.nz/","project":{"id":37,"url":"http://patchwork.ozlabs.org/api/projects/37/?format=json","name":"Devicetree Bindings","link_name":"devicetree-bindings","list_id":"devicetree.vger.kernel.org","list_email":"devicetree@vger.kernel.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20170927005516.28374-1-kalyan.kinthada@alliedtelesis.co.nz>","list_archive_url":null,"date":"2017-09-27T00:55:15","name":"[v2,0/1] Set FORCE_CSX bit when arbitration between NAND and NOR is enabled.","submitter":{"id":72417,"url":"http://patchwork.ozlabs.org/api/people/72417/?format=json","name":"Kalyan Kinthada","email":"kalyan.kinthada@alliedtelesis.co.nz"},"mbox":"http://patchwork.ozlabs.org/project/devicetree-bindings/cover/20170927005516.28374-1-kalyan.kinthada@alliedtelesis.co.nz/mbox/","series":[{"id":5258,"url":"http://patchwork.ozlabs.org/api/series/5258/?format=json","web_url":"http://patchwork.ozlabs.org/project/devicetree-bindings/list/?series=5258","date":"2017-09-27T00:55:15","name":"Set FORCE_CSX bit when arbitration between NAND and NOR is enabled.","version":2,"mbox":"http://patchwork.ozlabs.org/series/5258/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/covers/818877/comments/","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=alliedtelesis.co.nz\n\theader.i=@alliedtelesis.co.nz\n\theader.b=\"kfMjU5++\"; dkim-atps=neutral"],"Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3y1zrY5mh4z9t4Z\n\tfor ;\n\tWed, 27 Sep 2017 10:55:25 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S968296AbdI0AzX (ORCPT );\n\tTue, 26 Sep 2017 20:55:23 -0400","from gate2.alliedtelesis.co.nz ([202.36.163.20]:49742 \"EHLO\n\tgate2.alliedtelesis.co.nz\" rhost-flags-OK-OK-OK-OK) by\n\tvger.kernel.org with ESMTP id S936703AbdI0AzW (ORCPT\n\t); Tue, 26 Sep 2017 20:55:22 -0400","from mmarshal3.atlnz.lc (mmarshal3.atlnz.lc [10.32.18.43])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (Client did not present a certificate)\n\tby gate2.alliedtelesis.co.nz (Postfix) with ESMTPS id 1E042806A8;\n\tWed, 27 Sep 2017 13:55:20 +1300 (NZDT)","from smtp (Not Verified[10.32.16.33]) by mmarshal3.atlnz.lc with\n\tTrustwave SEG (v7, 5, 8, 10121)\n\tid ; Wed, 27 Sep 2017 13:55:20 +1300","from kalyank-dl.ws.atlnz.lc (kalyank-dl.ws.atlnz.lc [10.33.14.14])\n\tby smtp (Postfix) with ESMTP id 6769A13ED49;\n\tWed, 27 Sep 2017 13:55:29 +1300 (NZDT)","by kalyank-dl.ws.atlnz.lc (Postfix, from userid 1628)\n\tid E20F0C06DF; Wed, 27 Sep 2017 13:55:17 +1300 (NZDT)"],"DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed; d=alliedtelesis.co.nz; \n\ts=mail; t=1506473720;\n\tbh=IfDyt+yOJ2semeJ/lSQ82t843r57yi/3CZGbacHfdT0=;\n\th=From:To:Cc:Subject:Date;\n\tb=kfMjU5++4FVJ4MLzxyhgvRo0opkdmbQwZAyDTP1edIBc2gMoBFvzg6oWB4Hl+x3X1\n\ticvxm5td49xesCy6CTIbxxAyvIm4h67czYoI1zrOhCtoOLfp9MTLceh8LxvLiDEYTD\n\tBQ6TVa/RzcNBAm7KkKWjLHIKQClOzPaIzAZeYe9I=","From":"Kalyan Kinthada ","To":"dwmw2@infradead.org, computersforpeace@gmail.com,\n\tboris.brezillon@free-electrons.com, marek.vasut@gmail.com,\n\trichard@nod.at, cyrille.pitchen@wedev4u.fr, robh+dt@kernel.org,\n\tmark.rutland@arm.com, ezequiel.garcia@free-electrons.com,\n\tmiquel.raynal@free-electrons.com, devicetree@vger.kernel.org","Cc":"linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org,\n\tchris.packham@alliedtelesis.co.nz,\n\tKalyan Kinthada ","Subject":"[PATCH v2 0/1] Set FORCE_CSX bit when arbitration between NAND and\n\tNOR is enabled. ","Date":"Wed, 27 Sep 2017 13:55:15 +1300","Message-Id":"<20170927005516.28374-1-kalyan.kinthada@alliedtelesis.co.nz>","X-Mailer":"git-send-email 2.14.1","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"},"content":"When the arbitration between NOR and NAND flash is enabled\nthe field bit[21] in the Data Flash Control Register\nneeds to be set to 1 according to guidleine GL-5830741.\n\nSet the FORCE_CSX bit in NDCR for ARMADA370 variants as the arbitration\nis always enabled by default.\n\nChanges since v1:\n\nThanks Miquel RAYNAL for the suggestion.\n* Deleted: \"dt-bindings: mtd: pxa3xx: Add \"marvell,nand-force-csx\" compatible string\"\n Not necessary to create a new compatible string.\n\n* \"mtd-nand-pxa3xx-Set-FORCE_CSX-bit-to-ARMADA370-variants\" \n Modified commit message.\n This commit sets the FORCE_CSX bit for all ARMADA370 variants.\n\n----\nKalyan Kinthada (1):\n mtd: nand: pxa3xx: Set FORCE_CSX bit to ARMADA370 variants.\n\n drivers/mtd/nand/pxa3xx_nand.c | 7 +++++++\n 1 file changed, 7 insertions(+)"}