{"id":818381,"url":"http://patchwork.ozlabs.org/api/covers/818381/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-tegra/cover/cover.1506380746.git.digetx@gmail.com/","project":{"id":21,"url":"http://patchwork.ozlabs.org/api/projects/21/?format=json","name":"Linux Tegra Development","link_name":"linux-tegra","list_id":"linux-tegra.vger.kernel.org","list_email":"linux-tegra@vger.kernel.org","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"","list_archive_url":null,"date":"2017-09-25T23:22:01","name":"[v1,0/5] NVIDIA Tegra AHB DMA controller driver","submitter":{"id":18124,"url":"http://patchwork.ozlabs.org/api/people/18124/?format=json","name":"Dmitry Osipenko","email":"digetx@gmail.com"},"mbox":"http://patchwork.ozlabs.org/project/linux-tegra/cover/cover.1506380746.git.digetx@gmail.com/mbox/","series":[{"id":5029,"url":"http://patchwork.ozlabs.org/api/series/5029/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-tegra/list/?series=5029","date":"2017-09-25T23:22:01","name":"NVIDIA Tegra AHB DMA controller driver","version":1,"mbox":"http://patchwork.ozlabs.org/series/5029/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/covers/818381/comments/","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=linux-tegra-owner@vger.kernel.org;\n\treceiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=gmail.com header.i=@gmail.com\n\theader.b=\"l5bvsVw/\"; dkim-atps=neutral"],"Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3y1Kt5270pz9ryr\n\tfor ;\n\tTue, 26 Sep 2017 09:24:29 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S966161AbdIYXY1 (ORCPT );\n\tMon, 25 Sep 2017 19:24:27 -0400","from mail-wr0-f196.google.com ([209.85.128.196]:34368 \"EHLO\n\tmail-wr0-f196.google.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S965878AbdIYXYZ (ORCPT\n\t);\n\tMon, 25 Sep 2017 19:24:25 -0400","by mail-wr0-f196.google.com with SMTP id k20so918521wre.1;\n\tMon, 25 Sep 2017 16:24:24 -0700 (PDT)","from localhost.localdomain (ppp109-252-90-109.pppoe.spdop.ru.\n\t[109.252.90.109]) by smtp.gmail.com with ESMTPSA id\n\ta139sm1161965lfa.39.2017.09.25.16.24.22\n\t(version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128);\n\tMon, 25 Sep 2017 16:24:23 -0700 (PDT)"],"DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=gmail.com; s=20161025;\n\th=from:to:cc:subject:date:message-id;\n\tbh=7WoIMNbHQaVkPW2yMQc5FXX1Pn89Hp1ftX7Exm1xQLo=;\n\tb=l5bvsVw/qJ2S5fHGOhZmUd14H8Th2yJOcE0hTquP7EgrsHhvRZYcDphAPOIx/hbPVz\n\tR063hH6dGREOnt0z24KQWXpnnpDiRXBXFkU97iSjv9syZYynP+/sLGtHBbxyGa9+RRAM\n\tKoXWdq3wuaQjkq46tZvfGG0lf4ulADnO0oU+kBLntRiTpK0kKPTeWXL0hQuL4Uo0rQYd\n\tFuG++olWM2yB7hf6+FEWeqiNipnoGodeY7+PTFUw9XZUSrZvNiUrnUCjMVa8Zeqkb6DO\n\tZl9fyauNAlDpCKYXHskQ79apSGezQMqA9aytfm1WlNbIUHF5SkE/SP2ar9J/s5Rb4WKq\n\tlNmA==","X-Google-DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:from:to:cc:subject:date:message-id;\n\tbh=7WoIMNbHQaVkPW2yMQc5FXX1Pn89Hp1ftX7Exm1xQLo=;\n\tb=ENFzczPhz/t3fcBPXUmNqSA8Hyo9OX+PaO4GKRaV6AOEjx5RcGXcvuNwDxV+81IWKx\n\t5lmJ1eScI5+ramgrOxB9yXRWh8xpy7LaIh98MLFEBe4N4LtL+RCRAAG0j1HKe7JP+ucn\n\tAu2P/JU/K6t5DExPMC4/FIg2vr33MnsNnLawSkLYGOLL2GsU8NBspvuYJ2gK/7H9LngM\n\tmrfKlgZuxPNiGvM+AxLeI1TR+9ud6SXNy+q+tfR9FipTH3sB9GdyuwVS49Uy6G50P5xV\n\tquVYXe76juqkTBIHNlE0WnIvRy2iEuV40/s7yRDYGWTeXMJINaAXpGsAdtXMcXhinHkM\n\tua/g==","X-Gm-Message-State":"AHPjjUjQ7MxdxhWFHO1tb4mk5rFunTTpF8CIlq4DQSv8dq7mvjPooD4R\n\t+FOtqVjecR66kw2nzWMd0MY=","X-Google-Smtp-Source":"AOwi7QC/C50ADZCUUvNkHzRNkPlmv/lfr3Ev4WqlBd1EaSoi92xquM2HdkJdbPVVfD4D7Du+j3wERw==","X-Received":"by 10.46.25.78 with SMTP id p75mr3220658lje.24.1506381864129;\n\tMon, 25 Sep 2017 16:24:24 -0700 (PDT)","From":"Dmitry Osipenko ","To":"Thierry Reding ,\n\tJonathan Hunter ,\n\tLaxman Dewangan ,\n\tPeter De Schrijver ,\n\tPrashant Gaikwad ,\n\tMichael Turquette ,\n\tStephen Boyd , Rob Herring ,\n\tVinod Koul ","Cc":"linux-tegra@vger.kernel.org, devicetree@vger.kernel.org,\n\tdmaengine@vger.kernel.org, linux-clk@vger.kernel.org,\n\tlinux-kernel@vger.kernel.org","Subject":"[PATCH v1 0/5] NVIDIA Tegra AHB DMA controller driver","Date":"Tue, 26 Sep 2017 02:22:01 +0300","Message-Id":"","X-Mailer":"git-send-email 2.14.1","Sender":"linux-tegra-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"linux-tegra@vger.kernel.org"},"content":"NVIDIA Tegra20/30 SoC's have AHB DMA controller. It has 4 DMA channels,\nsupports AHB <-> Memory and Memory <-> Memory transfers, slave / master\nmodes. This driver is primarily supposed to be used by gpu/host1x in a\nmaster mode, performing 3D HW context stores.\n\nDmitry Osipenko (5):\n clk: tegra: Add AHB DMA clock entry\n clk: tegra: Bump SCLK clock rate to 216MHz on Tegra20\n dt-bindings: Add DT bindings for NVIDIA Tegra AHB DMA controller\n dmaengine: Add driver for NVIDIA Tegra AHB DMA controller\n ARM: dts: tegra: Add AHB DMA controller nodes\n\n .../bindings/dma/nvidia,tegra20-ahbdma.txt | 23 +\n arch/arm/boot/dts/tegra20.dtsi | 9 +\n arch/arm/boot/dts/tegra30.dtsi | 9 +\n drivers/clk/tegra/clk-id.h | 1 +\n drivers/clk/tegra/clk-tegra-periph.c | 1 +\n drivers/clk/tegra/clk-tegra20.c | 8 +-\n drivers/clk/tegra/clk-tegra30.c | 2 +\n drivers/dma/Kconfig | 9 +\n drivers/dma/Makefile | 1 +\n drivers/dma/tegra20-ahb-dma.c | 679 +++++++++++++++++++++\n 10 files changed, 741 insertions(+), 1 deletion(-)\n create mode 100644 Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt\n create mode 100644 drivers/dma/tegra20-ahb-dma.c"}