{"id":817557,"url":"http://patchwork.ozlabs.org/api/covers/817557/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/cover/1506092407-26985-1-git-send-email-peter.maydell@linaro.org/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<1506092407-26985-1-git-send-email-peter.maydell@linaro.org>","list_archive_url":null,"date":"2017-09-22T14:59:47","name":"[00/20] ARM v8M: exception entry, exit and security","submitter":{"id":5111,"url":"http://patchwork.ozlabs.org/api/people/5111/?format=json","name":"Peter Maydell","email":"peter.maydell@linaro.org"},"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/cover/1506092407-26985-1-git-send-email-peter.maydell@linaro.org/mbox/","series":[{"id":4650,"url":"http://patchwork.ozlabs.org/api/series/4650/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=4650","date":"2017-09-22T14:59:47","name":"ARM v8M: exception entry, exit and security","version":1,"mbox":"http://patchwork.ozlabs.org/series/4650/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/covers/817557/comments/","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=)","Received":["from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xzGqq5lCvz9sNr\n\tfor ;\n\tSat, 23 Sep 2017 01:00:23 +1000 (AEST)","from localhost ([::1]:59302 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t)\n\tid 1dvPRF-0007uz-RG\n\tfor incoming@patchwork.ozlabs.org; Fri, 22 Sep 2017 11:00:21 -0400","from eggs.gnu.org ([2001:4830:134:3::10]:46834)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from ) id 1dvPQV-0007sX-1l\n\tfor qemu-devel@nongnu.org; Fri, 22 Sep 2017 10:59:36 -0400","from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from ) id 1dvPQU-000415-B0\n\tfor qemu-devel@nongnu.org; Fri, 22 Sep 2017 10:59:35 -0400","from orth.archaic.org.uk ([2001:8b0:1d0::2]:37534)\n\tby eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32)\n\t(Exim 4.71) (envelope-from )\n\tid 1dvPQS-0003yz-7z; Fri, 22 Sep 2017 10:59:32 -0400","from pm215 by orth.archaic.org.uk with local (Exim 4.89)\n\t(envelope-from )\n\tid 1dvPQP-00077k-SZ; Fri, 22 Sep 2017 15:59:29 +0100"],"From":"Peter Maydell ","To":"qemu-arm@nongnu.org,\n\tqemu-devel@nongnu.org","Date":"Fri, 22 Sep 2017 15:59:47 +0100","Message-Id":"<1506092407-26985-1-git-send-email-peter.maydell@linaro.org>","X-Mailer":"git-send-email 2.7.4","X-detected-operating-system":"by eggs.gnu.org: Genre and OS details not\n\trecognized.","X-Received-From":"2001:8b0:1d0::2","Subject":"[Qemu-devel] [PATCH 00/20] ARM v8M: exception entry,\n\texit and security","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"patches@linaro.org","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"\"Qemu-devel\"\n\t"},"content":"Another week, another set of v8M patches.\nThis lot adds:\n * v8M and security extension changes in exception entry and exit\n * the Security Attribution Unit\n * SG and BLXNS instructions\n * secure function return\n * and a couple of fixes for bugs in already-in-master changes\n\nMost of this is just plodding through fairly obvious implementation,\nbut the handling of the SG instruction is a bit funky (see commit\nmessages in those patches for detail).\n\nThis is very nearly enough to get the mbed uvisor example\nrunning (on a hacked-up mps2 setup): I think the main missing\npiece for that is that it expects the banked systick device,\nwhich we haven't implemented yet. (There are also various\nmissing things that I don't think the uvisor exercises.)\n\nthanks\n-- PMM\n\nPeter Maydell (20):\n nvic: Clear the vector arrays and prigroup on reset\n target/arm: Don't switch to target stack early in v7M exception return\n target/arm: Prepare for CONTROL.SPSEL being nonzero in Handler mode\n target/arm: Restore security state on exception return\n target/arm: Restore SPSEL to correct CONTROL register on exception\n return\n target/arm: Check for xPSR mismatch usage faults earlier for v8M\n target/arm: Warn about restoring to unaligned stack\n target/arm: Don't warn about exception return with PC low bit set for\n v8M\n target/arm: Add new-in-v8M SFSR and SFAR\n target/arm: Update excret sanity checks for v8M\n target/arm: Add support for restoring v8M additional state context\n target/arm: Add v8M support to exception entry code\n nvic: Implement Security Attribution Unit registers\n target/arm: Implement security attribute lookups for memory accesses\n target/arm: Fix calculation of secure mm_idx values\n target/arm: Factor out \"get mmuidx for specified security state\"\n target/arm: Implement SG instruction\n target/arm: Implement BLXNS\n target/arm: Implement secure function return\n nvic: Add missing code for writing SHCSR.HARDFAULTPENDED bit\n\n target/arm/cpu.h | 60 ++-\n target/arm/helper.h | 1 +\n target/arm/internals.h | 23 ++\n hw/intc/armv7m_nvic.c | 158 +++++++-\n target/arm/cpu.c | 27 ++\n target/arm/helper.c | 970 ++++++++++++++++++++++++++++++++++++++++++++-----\n target/arm/machine.c | 16 +\n target/arm/translate.c | 31 +-\n 8 files changed, 1181 insertions(+), 105 deletions(-)"}