{"id":817025,"url":"http://patchwork.ozlabs.org/api/covers/817025/?format=json","web_url":"http://patchwork.ozlabs.org/project/devicetree-bindings/cover/20170921164940.20343-1-georgi.djakov@linaro.org/","project":{"id":37,"url":"http://patchwork.ozlabs.org/api/projects/37/?format=json","name":"Devicetree Bindings","link_name":"devicetree-bindings","list_id":"devicetree.vger.kernel.org","list_email":"devicetree@vger.kernel.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20170921164940.20343-1-georgi.djakov@linaro.org>","list_archive_url":null,"date":"2017-09-21T16:49:33","name":"[v9,0/7] Add support for Qualcomm A53 CPU clock","submitter":{"id":70295,"url":"http://patchwork.ozlabs.org/api/people/70295/?format=json","name":"Georgi Djakov","email":"georgi.djakov@linaro.org"},"mbox":"http://patchwork.ozlabs.org/project/devicetree-bindings/cover/20170921164940.20343-1-georgi.djakov@linaro.org/mbox/","series":[{"id":4442,"url":"http://patchwork.ozlabs.org/api/series/4442/?format=json","web_url":"http://patchwork.ozlabs.org/project/devicetree-bindings/list/?series=4442","date":"2017-09-21T16:49:33","name":"Add support for Qualcomm A53 CPU clock","version":9,"mbox":"http://patchwork.ozlabs.org/series/4442/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/covers/817025/comments/","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=linaro.org header.i=@linaro.org\n\theader.b=\"BPJFI/jL\"; dkim-atps=neutral"],"Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xyjJY4SC8z9t3C\n\tfor ;\n\tFri, 22 Sep 2017 02:49:49 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751581AbdIUQtq (ORCPT\n\t);\n\tThu, 21 Sep 2017 12:49:46 -0400","from mail-wm0-f54.google.com ([74.125.82.54]:45378 \"EHLO\n\tmail-wm0-f54.google.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1751687AbdIUQtn (ORCPT\n\t); Thu, 21 Sep 2017 12:49:43 -0400","by mail-wm0-f54.google.com with SMTP id q124so3600201wmb.0\n\tfor ;\n\tThu, 21 Sep 2017 09:49:42 -0700 (PDT)","from mms-0441.qualcomm.mm-sol.com ([212.45.67.2])\n\tby smtp.googlemail.com with ESMTPSA id\n\ti16sm993311edj.29.2017.09.21.09.49.40\n\t(version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128);\n\tThu, 21 Sep 2017 09:49:41 -0700 (PDT)"],"DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google;\n\th=from:to:cc:subject:date:message-id;\n\tbh=SFNcM/ZuJLY1MKI1U6mE8IMlhEogwP/OxT/FNS/9ZIU=;\n\tb=BPJFI/jLasXsTJE9uCrdIKyVK4w+JqdX3ppqab/JZuin8OHz7eXfya9ATACvYoAgb/\n\tuSupqWXzYKDDTOv/7Ku8h2mRIBj/bMVLewXiTc1itpdwOxDSAjW+qrYKUiPdVI3u9d7m\n\tzOrDl++Zv0xb0hTih9kLTGlYob7G8spxTQ+mA=","X-Google-DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:from:to:cc:subject:date:message-id;\n\tbh=SFNcM/ZuJLY1MKI1U6mE8IMlhEogwP/OxT/FNS/9ZIU=;\n\tb=l4ZINvH3xcFCGI6V/NLTbimMNf9HWdnOdWKVDXiscCKCiFmZiZQJ9fZPRjN8waTJ4h\n\tVYfSFl3d5Mz93/hFGXeAK+BeAhEEf19GNaslE6zeBoFH15D3GlK1xp9etZnBC+X9S2rk\n\t/ro0v+jLR1X0VmoliDRl9Hs/tfmjGFPwUQk9x7pC060zU9l0FFL8VqogupAMJCaA19k3\n\tOZt/1ULRlzouu/N/SgZi2C7QB+VwrBoFy6T2wOrcMZ3HQf1DIqkS8uWBzs23SGcuyLBl\n\tpr/uPNgNRlxozc9MjYXYWa2igYNSUpNDCuNDgTd2W7s9SZdqhSEu9M4KSb8Wba1Swt0p\n\tg3DQ==","X-Gm-Message-State":"AHPjjUh7ZXIV3W4lNar0Ad5IvzuGhlmo9Auk1K1+2XEZF7s4r+HUSZwi\n\tBzQ0t41Jy0PGsqVapeZforAG0A==","X-Google-Smtp-Source":"AOwi7QCO1+O38oH3LNw2hM1jyrtS2n2OGoLELrg6eJNdGmIom9B9lC8KTfXw+f2NYwFVwq0biS+Xhg==","X-Received":"by 10.80.151.206 with SMTP id f14mr1862556edb.27.1506012582112; \n\tThu, 21 Sep 2017 09:49:42 -0700 (PDT)","From":"Georgi Djakov ","To":"sboyd@codeaurora.org, jassisinghbrar@gmail.com,\n\tbjorn.andersson@linaro.org, robh+dt@kernel.org","Cc":"mturquette@baylibre.com, linux-clk@vger.kernel.org,\n\tlinux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org,\n\tdevicetree@vger.kernel.org, georgi.djakov@linaro.org","Subject":"[PATCH v9 0/7] Add support for Qualcomm A53 CPU clock","Date":"Thu, 21 Sep 2017 19:49:33 +0300","Message-Id":"<20170921164940.20343-1-georgi.djakov@linaro.org>","X-Mailer":"git-send-email 2.14.1","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"},"content":"This patchset adds support for the A53 CPU clock on MSM8916 platforms\nand allows scaling of the CPU frequency on msm8916 based platforms.\n\nChanges since v8 (https://lkml.org/lkml/2017/6/23/476)\n * Converted APCS mailbox driver to use regmap and to populate child\n platform devices that will handle the rest of the functionality\n provided by APCS block.\n * Picked Rob's Ack for the PLL binding.\n * Changed the APCS binding and put it into a separate patch.\n * Addressed review comments.\n * Minor changes.\n\nChanges since v7 (https://lkml.org/lkml/2016/10/31/296)\n * Add the APCS clock controller to the APCS driver to expose both the\n mailbox and clock controller functionality as discussed earlier:\n https://lkml.org/lkml/2016/11/14/860\n * Changed the a53pll compatible string as suggested by Rob.\n\nChanges since v6 (https://lkml.org/lkml/2016/9/7/347)\n * Addressed various comments from Stephen Boyd\n\nChanges since v5 (https://lkml.org/lkml/2016/2/1/407)\n * Rebase to clk-next and update according to the recent API changes.\n\nChanges since v4 (https://lkml.org/lkml/2015/12/14/367)\n * Convert to builtin drivers as now __clk_lookup() is used\n\nChanges since v3 (https://lkml.org/lkml/2015/8/12/585)\n * Split driver into two parts - and separate A53 PLL and\n A53 clock controller drivers.\n * Drop the safe switch hook patch. Add a clock notifier in\n the clock provider to handle switching via safe mux and\n divider configuration.\n\nChanges since v2 (https://lkml.org/lkml/2015/7/24/526)\n * Drop gpll0_vote patch.\n * Switch to the new clk_hw_* APIs.\n * Rebase to the current clk-next.\n\nChanges since v1 (https://lkml.org/lkml/2015/6/12/193)\n * Drop SR2 PLL patch, as it is already applied.\n * Add gpll0_vote rate propagation patch.\n * Update/rebase patches to the current clk-next.\n\n\nGeorgi Djakov (7):\n mailbox: qcom: Convert APCS IPC driver to use regmap\n mailbox: qcom: Populate APCS child platform devices\n mailbox: qcom: Move the apcs struct into a separate header\n clk: qcom: Add A53 PLL support\n clk: qcom: Add regmap mux-div clocks support\n dt-bindings: clock: Document qcom,apcs binding\n clk: qcom: Add APCS clock controller support\n\n .../devicetree/bindings/clock/qcom,a53pll.txt | 22 ++\n .../devicetree/bindings/clock/qcom,apcs.txt | 27 +++\n drivers/clk/qcom/Kconfig | 21 ++\n drivers/clk/qcom/Makefile | 3 +\n drivers/clk/qcom/a53-pll.c | 107 ++++++++++\n drivers/clk/qcom/apcs-msm8916.c | 172 +++++++++++++++\n drivers/clk/qcom/clk-regmap-mux-div.c | 237 +++++++++++++++++++++\n drivers/clk/qcom/clk-regmap-mux-div.h | 54 +++++\n drivers/mailbox/qcom-apcs-ipc-mailbox.c | 36 ++--\n include/linux/mailbox/qcom-apcs.h | 34 +++\n 10 files changed, 700 insertions(+), 13 deletions(-)\n create mode 100644 Documentation/devicetree/bindings/clock/qcom,a53pll.txt\n create mode 100644 Documentation/devicetree/bindings/clock/qcom,apcs.txt\n create mode 100644 drivers/clk/qcom/a53-pll.c\n create mode 100644 drivers/clk/qcom/apcs-msm8916.c\n create mode 100644 drivers/clk/qcom/clk-regmap-mux-div.c\n create mode 100644 drivers/clk/qcom/clk-regmap-mux-div.h\n create mode 100644 include/linux/mailbox/qcom-apcs.h\n\n--\nTo unsubscribe from this list: send the line \"unsubscribe devicetree\" in\nthe body of a message to majordomo@vger.kernel.org\nMore majordomo info at http://vger.kernel.org/majordomo-info.html"}