{"id":816954,"url":"http://patchwork.ozlabs.org/api/covers/816954/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/cover/1506007346-10037-1-git-send-email-jjhiblot@ti.com/","project":{"id":18,"url":"http://patchwork.ozlabs.org/api/projects/18/?format=json","name":"U-Boot","link_name":"uboot","list_id":"u-boot.lists.denx.de","list_email":"u-boot@lists.denx.de","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<1506007346-10037-1-git-send-email-jjhiblot@ti.com>","list_archive_url":null,"date":"2017-09-21T15:22:03","name":"[U-Boot,00/23] mmc: omap5: Add support for UHS and HS200 modes","submitter":{"id":70508,"url":"http://patchwork.ozlabs.org/api/people/70508/?format=json","name":"Jean-Jacques Hiblot","email":"jjhiblot@ti.com"},"mbox":"http://patchwork.ozlabs.org/project/uboot/cover/1506007346-10037-1-git-send-email-jjhiblot@ti.com/mbox/","series":[{"id":4414,"url":"http://patchwork.ozlabs.org/api/series/4414/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/list/?series=4414","date":"2017-09-21T15:22:03","name":"mmc: omap5: Add support for UHS and HS200 modes","version":1,"mbox":"http://patchwork.ozlabs.org/series/4414/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/covers/816954/comments/","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=ti.com header.i=@ti.com header.b=\"HJlpzJBd\";\n\tdkim-atps=neutral"],"Received":["from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 3xygND1TXtz9t3w\n\tfor ;\n\tFri, 22 Sep 2017 01:22:50 +1000 (AEST)","by lists.denx.de (Postfix, from userid 105)\n\tid 63D5EC2201C; Thu, 21 Sep 2017 15:22:47 +0000 (UTC)","from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id CAC8EC21C54;\n\tThu, 21 Sep 2017 15:22:44 +0000 (UTC)","by lists.denx.de (Postfix, from userid 105)\n\tid A698EC21C54; Thu, 21 Sep 2017 15:22:42 +0000 (UTC)","from lelnx193.ext.ti.com (lelnx193.ext.ti.com [198.47.27.77])\n\tby lists.denx.de (Postfix) with ESMTPS id 07197C21C4E\n\tfor ; Thu, 21 Sep 2017 15:22:41 +0000 (UTC)","from dflxv15.itg.ti.com ([128.247.5.124])\n\tby lelnx193.ext.ti.com (8.15.1/8.15.1) with ESMTP id v8LFMdQ3007896; \n\tThu, 21 Sep 2017 10:22:39 -0500","from DLEE102.ent.ti.com (dlee102.ent.ti.com [157.170.170.32])\n\tby dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id v8LFMdkN009250;\n\tThu, 21 Sep 2017 10:22:39 -0500","from DLEE107.ent.ti.com (157.170.170.37) by DLEE102.ent.ti.com\n\t(157.170.170.32) with Microsoft SMTP Server (version=TLS1_2,\n\tcipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id 15.1.845.34;\n\tThu, 21 Sep 2017 10:22:39 -0500","from dflp32.itg.ti.com (10.64.6.15) by DLEE107.ent.ti.com\n\t(157.170.170.37) with Microsoft SMTP Server (version=TLS1_0,\n\tcipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.845.34 via Frontend\n\tTransport; Thu, 21 Sep 2017 10:22:39 -0500","from localhost (ileax41-snat.itg.ti.com [10.172.224.153])\n\tby dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id v8LFMcEk014656;\n\tThu, 21 Sep 2017 10:22:38 -0500"],"X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de","X-Spam-Level":"","X-Spam-Status":"No, score=0.0 required=5.0 tests=RCVD_IN_DNSWL_NONE,\n\tT_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0","DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com;\n\ts=ti-com-17Q1; t=1506007359;\n\tbh=3YYwjtDDahpzyr7+waGGxpbCzQtsoSkCaE5FKhhtAHY=;\n\th=From:To:CC:Subject:Date;\n\tb=HJlpzJBdC7uE54e8QAOkQ7b0qQNYz5bs9s3yYuX7BP612Z+Fxz1HzQIiooS/GEqrN\n\tdrIEjcZkhG0KOAVzKEoJMEpyb4PeaQW8hXgZKMeHC1G/y+WRE/Wzuiiq5t3Iow/1x6\n\tIFvy2YRmT+xfTSdKNYFED/CUZXJMkUR7EnBsnpXM=","From":"Jean-Jacques Hiblot ","To":", , ,\n\t, ","Date":"Thu, 21 Sep 2017 17:22:03 +0200","Message-ID":"<1506007346-10037-1-git-send-email-jjhiblot@ti.com>","X-Mailer":"git-send-email 1.9.1","MIME-Version":"1.0","X-EXCLAIMER-MD-CONFIG":"e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180","Cc":"u-boot@lists.denx.de","Subject":"[U-Boot] [PATCH 00/23] mmc: omap5: Add support for UHS and HS200\n\tmodes","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.18","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" "},"content":"This series adds the missing bit to enable the UHS, HS200 and DDR52 modes\non the omap5 platforms (DRA7 and AM57).\n\nIt relies on the following series:\n* [PATCH v2 00/26] mmc: Add support for HS200 and UHS modes\n* [PATCH v2 0/5] mmc: omap_hsmmc: Add support for ADMA\n* [PATCH v3 0/2] power: Add a driver to handle the PBIAS cell of the TI SOCs\n\nEnabling support for high speed modes on omap5 requires implementing:\n * io signal voltage selection\n * tuning support\n * pin configuration (IO delays)\n \nThe few last patches enable the high mode for all omap5 platforms except some\nfor which we need to disable either the UHS or the HS200 because the volatge\nregulators on board would not allow using those modes. This is not a SOC\nlimitation.\n\nWith this in place we observe significant improvements in the performances:\non a DRA72 evm:\neMMC HS200: 124 MB/s\neMMC DDR52: 78 MB/s\nsd SDR104: 71 MB/s\nsd SDR50: 44 MB/s\nFor the record, the original performances were:\nSD High speed: 18 MB/s\nMMC High speed: 18 MB/s\n\nThis series has been tested on:\n* DRA71-evm\n* DRA72-evm\n* DRA7x-evm\n* DRA76-evm\n* AM57x-evm\n* Beaglebone Black\n* AM335x evm\n* AM437x SK\n\nJean-Jacques\n \n\n\nJean-Jacques Hiblot (8):\n mmc: omap_hsmmc: Reduce the max timeout for reset controller fsm\n mmc: omap_hsmmc: allow the simple HS modes to use the default pinctrl\n mmc: omap_hsmmc: update mmc->clock with the actual bus speed\n mmc: omap_hsmmc: implement send_init_stream callback\n mmc: omap_hsmmc: add signal voltage selection support\n ARM: dts: dra7: Add supported MMC/SD modes in MMC dt nodes\n dts: am57xx-beagle-x15: disable UHS and HS200 support\n dts: am57xx-idk: disable HS200 support\n\nKishon Vijay Abraham I (15):\n mmc: omap_hsmmc: cleanup clock configuration\n mmc: omap_hsmmc: cleanup omap_hsmmc_set_ios\n mmc: omap_hsmmc: add support to set default io voltage\n mmc: omap_hsmmc: set MMC mode in the UHSMS bit field\n mmc: omap_hsmmc: Enable DDR mode support\n mmc: omap_hsmmc: Add tuning support\n mmc: omap_hsmmc: Workaround for errata id i802\n mmc: omap_hsmmc: use mmc_of_parse to populate mmc_config\n ARM: OMAP5/DRA7: Enable iodelay recalibration to be done from uboot\n mmc: omap_hsmmc: Add support to set IODELAY values\n mmc: omap_hsmmc: Add support to get pinctrl values and max frequency\n for different hw revisions\n mmc: omap_hsmmc: allow mmc clock to be gated\n ARM: OMAP5: set mmc clock frequency to 192MHz\n ARM: dts: DRA7: use new dra7-specific compatible string\n ARM: DRA7x/AM57x: Add MMC/SD fixups for rev1.0 and rev 1.1\n\n arch/arm/dts/am57xx-beagle-x15.dts | 6 +\n arch/arm/dts/am57xx-idk-common.dtsi | 2 +\n arch/arm/dts/dra7.dtsi | 22 +-\n arch/arm/include/asm/arch-omap5/clock.h | 2 +-\n arch/arm/include/asm/arch-omap5/dra7xx_iodelay.h | 3 +\n arch/arm/include/asm/arch-omap5/sys_proto.h | 7 +\n arch/arm/include/asm/omap_mmc.h | 59 +-\n arch/arm/mach-omap2/omap5/dra7xx_iodelay.c | 30 +\n arch/arm/mach-omap2/omap5/hw_data.c | 10 +-\n board/ti/am57xx/board.c | 30 +\n board/ti/dra7xx/evm.c | 29 +\n drivers/mmc/omap_hsmmc.c | 940 +++++++++++++++++++++--\n include/configs/am57xx_evm.h | 2 -\n include/configs/dra7xx_evm.h | 2 -\n 14 files changed, 1071 insertions(+), 73 deletions(-)"}