{"id":816394,"url":"http://patchwork.ozlabs.org/api/covers/816394/?format=json","web_url":"http://patchwork.ozlabs.org/project/devicetree-bindings/cover/1505932139-2905-1-git-send-email-matthew.gerlach@linux.intel.com/","project":{"id":37,"url":"http://patchwork.ozlabs.org/api/projects/37/?format=json","name":"Devicetree Bindings","link_name":"devicetree-bindings","list_id":"devicetree.vger.kernel.org","list_email":"devicetree@vger.kernel.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<1505932139-2905-1-git-send-email-matthew.gerlach@linux.intel.com>","list_archive_url":null,"date":"2017-09-20T18:28:56","name":"[v2,0/3] Altera ASMI Parallel II IP Core","submitter":{"id":70992,"url":"http://patchwork.ozlabs.org/api/people/70992/?format=json","name":"Matthew Gerlach","email":"matthew.gerlach@linux.intel.com"},"mbox":"http://patchwork.ozlabs.org/project/devicetree-bindings/cover/1505932139-2905-1-git-send-email-matthew.gerlach@linux.intel.com/mbox/","series":[{"id":4191,"url":"http://patchwork.ozlabs.org/api/series/4191/?format=json","web_url":"http://patchwork.ozlabs.org/project/devicetree-bindings/list/?series=4191","date":"2017-09-20T18:28:57","name":"Altera ASMI Parallel II IP Core","version":2,"mbox":"http://patchwork.ozlabs.org/series/4191/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/covers/816394/comments/","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xy7Zn5yB7z9s7m\n\tfor ;\n\tThu, 21 Sep 2017 04:30:09 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751606AbdITS3H (ORCPT\n\t);\n\tWed, 20 Sep 2017 14:29:07 -0400","from mga09.intel.com ([134.134.136.24]:53365 \"EHLO mga09.intel.com\"\n\trhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP\n\tid S1751554AbdITS3G (ORCPT );\n\tWed, 20 Sep 2017 14:29:06 -0400","from orsmga002.jf.intel.com ([10.7.209.21])\n\tby orsmga102.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t20 Sep 2017 11:29:06 -0700","from mgerlach-mobl.amr.corp.intel.com (HELO\n\tmgerlach-VirtualBox.amr.corp.intel.com) ([10.254.74.152])\n\tby orsmga002.jf.intel.com with ESMTP; 20 Sep 2017 11:29:05 -0700"],"X-ExtLoop1":"1","X-IronPort-AV":"E=Sophos;i=\"5.42,422,1500966000\"; d=\"scan'208\";a=\"137603164\"","From":"matthew.gerlach@linux.intel.com","To":"vndao@altera.com, dwmw2@infradead.org, computersforpeace@gmail.com,\n\tboris.brezillon@free-electrons.com, marek.vasut@gmail.com,\n\trichard@nod.at, cyrille.pitchen@wedev4u.fr, robh+dt@kernel.org,\n\tmark.rutland@arm.com, linux-mtd@lists.infradead.org,\n\tdevicetree@vger.kernel.org, linux-kernel@vger.kernel.org,\n\tgregkh@linuxfoundation.org, davem@davemloft.net,\n\tmchehab@kernel.org, linux-fpga@vger.kernel.org,\n\ttien.hock.loh@intel.com, hean.loong.ong@intel.com","Cc":"Matthew Gerlach ","Subject":"[PATCH v2 0/3] Altera ASMI Parallel II IP Core","Date":"Wed, 20 Sep 2017 11:28:56 -0700","Message-Id":"<1505932139-2905-1-git-send-email-matthew.gerlach@linux.intel.com>","X-Mailer":"git-send-email 2.7.4","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"},"content":"From: Matthew Gerlach \n\nThis patch set adds a spi-nor flash driver for the Altera ASMI Parallel II \nIP Core. This driver was created based on feedback from Marek Vasut,\nCyrill Pitchen, and Michal Suchanek regarding Version 2 of the Altera\nQuadspi Controller: https://lkml.org/lkml/2017/6/26/518\n\nThe overall problem with Version 2 of the Altera Quadspi Controller and \nits driver was the fact that there was much duplication of code and logic\nwith the spi-nor framework. This new combination of fpga hardware and \nsoftware \"gets out of the way\" of the spi-nor framework. The result is a\nmuch simpler driver with the spi-nor framework performing the bulk of the work.\n\nPatch 1 contains the device tree bindings for the driver for\nthe Altera ASMI-Parallel II IP Core.\n\nPatch 2 contains the driver code for the Altera ASMI-Parallel II IP Core.\nThis driver supports being configured via a device tree or with platform\ndata. In the later case, the memory for the registers has been remapped.\n\nPatch 3 contains a work around for some non-standard behavior of EPCQ flash.\n\nMatthew Gerlach (3):\n dt-bindings: mtd: Altera ASMI Parallel II IP Core\n mtd: spi-nor: Altera ASMI Parallel II IP Core\n mtd: spi-nor: add flag for reading dummy cycles from nv cfg reg\n\n .../devicetree/bindings/mtd/altera-asmip2.txt | 15 +\n MAINTAINERS | 7 +\n drivers/mtd/spi-nor/Kconfig | 6 +\n drivers/mtd/spi-nor/Makefile | 1 +\n drivers/mtd/spi-nor/altera-asmip2.c | 478 +++++++++++++++++++++\n include/linux/mtd/altera-asmip2.h | 27 ++\n 6 files changed, 534 insertions(+)\n create mode 100644 Documentation/devicetree/bindings/mtd/altera-asmip2.txt\n create mode 100644 drivers/mtd/spi-nor/altera-asmip2.c\n create mode 100644 include/linux/mtd/altera-asmip2.h"}