{"id":816113,"url":"http://patchwork.ozlabs.org/api/covers/816113/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-imx/cover/cover.1505890481.git.sean.wang@mediatek.com/","project":{"id":19,"url":"http://patchwork.ozlabs.org/api/projects/19/?format=json","name":"Linux IMX development","link_name":"linux-imx","list_id":"linux-imx-kernel.lists.patchwork.ozlabs.org","list_email":"linux-imx-kernel@lists.patchwork.ozlabs.org","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<cover.1505890481.git.sean.wang@mediatek.com>","list_archive_url":null,"date":"2017-09-20T09:49:24","name":"[0/4] add support of clock driver on MediaTek MT7622","submitter":{"id":69660,"url":"http://patchwork.ozlabs.org/api/people/69660/?format=json","name":"Sean Wang","email":"sean.wang@mediatek.com"},"mbox":"http://patchwork.ozlabs.org/project/linux-imx/cover/cover.1505890481.git.sean.wang@mediatek.com/mbox/","series":[{"id":4068,"url":"http://patchwork.ozlabs.org/api/series/4068/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-imx/list/?series=4068","date":"2017-09-20T09:49:24","name":"add support of clock driver on MediaTek MT7622","version":1,"mbox":"http://patchwork.ozlabs.org/series/4068/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/covers/816113/comments/","headers":{"Return-Path":"<linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org>","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; 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Wed, 20 Sep 2017 17:49:28 +0800","from mtkcas09.mediatek.inc (172.21.101.178) by\n\tmtkmbs08n2.mediatek.inc (172.21.101.56) with Microsoft SMTP Server\n\t(TLS) id 15.0.1210.3; Wed, 20 Sep 2017 17:49:13 +0800","from mtkswgap22.mediatek.inc (172.21.77.33) by\n\tmtkcas09.mediatek.inc\n\t(172.21.101.73) with Microsoft SMTP Server id 15.0.1210.3 via\n\tFrontend Transport; Wed, 20 Sep 2017 17:49:46 +0800"],"DKIM-Signature":"v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed;\n\td=lists.infradead.org; s=bombadil.20170209; h=Sender:\n\tContent-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post:\n\tList-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-ID:Date:Subject:To\n\t:From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From:\n\tResent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References:\n\tList-Owner; bh=TBn88RNQsVvR+M2+W7Y90nkuLatM+o3WTgmDF1rnGss=;\n\tb=dM2c3y+YFsx6W5\n\tL9FpvIXasyRqKKJ6ynoIeCCFTmrQeF46UkAzGIGdBQwW3+soDE6l5lfzPflYBMNjQGLnrg278lfE9\n\tPRF7YNHK/7U328+rGRwlLDovfWsCeF/obWP53WZVAaEog5xms9u9IIWeFhSDRLzgZ9sUEYchRYR3+\n\t00ja4xx3ZjITW9BJqXgMbhLCgv07p4JcYnKI/YiFE4rhwahFV1nFFDQhXW6giDDLg4M4/p/+O8zpW\n\t5Wg51Rg7RidG9c+7Rhj3NXnbveaunQnyd+9lyvfofi2bkDs8mX2/5NumzK+5Txksnq7zxbu91mEmO\n\tVsJRiND0BWlHe0T/HcQA==;","X-UUID":"f323327e812045e382b9d482b5ca24f5-20170920","From":"<sean.wang@mediatek.com>","To":"<sboyd@codeaurora.org>, <mturquette@baylibre.com>, <robh+dt@kernel.org>, \n\t<matthias.bgg@gmail.com>, <mark.rutland@arm.com>,\n\t<p.zabel@pengutronix.de>","Subject":"[PATCH 0/4] add support of clock driver on MediaTek MT7622","Date":"Wed, 20 Sep 2017 17:49:24 +0800","Message-ID":"<cover.1505890481.git.sean.wang@mediatek.com>","X-Mailer":"git-send-email 1.7.9.5","MIME-Version":"1.0","X-MTK":"N","X-CRM114-Version":"20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ","X-CRM114-CacheID":"sfid-20170920_024958_548534_DFFFD78B ","X-CRM114-Status":"UNSURE (   8.40  )","X-CRM114-Notice":"Please train this message.","X-Spam-Score":"-1.1 (-)","X-Spam-Report":"SpamAssassin version 3.4.1 on bombadil.infradead.org summary:\n\tContent analysis details:   (-1.1 points)\n\tpts rule name              description\n\t---- ----------------------\n\t--------------------------------------------------\n\t-0.0 SPF_PASS               SPF: sender matches SPF record\n\t-1.9 BAYES_00               BODY: Bayes spam probability is 0 to 1%\n\t[score: 0.0000]\n\t0.8 RDNS_NONE Delivered to internal network by a host with no rDNS\n\t0.0 UNPARSEABLE_RELAY Informational: message has unparseable relay\n\tlines","X-BeenThere":"linux-arm-kernel@lists.infradead.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Unsubscribe":"<http://lists.infradead.org/mailman/options/linux-arm-kernel>,\n\t<mailto:linux-arm-kernel-request@lists.infradead.org?subject=unsubscribe>","List-Archive":"<http://lists.infradead.org/pipermail/linux-arm-kernel/>","List-Post":"<mailto:linux-arm-kernel@lists.infradead.org>","List-Help":"<mailto:linux-arm-kernel-request@lists.infradead.org?subject=help>","List-Subscribe":"<http://lists.infradead.org/mailman/listinfo/linux-arm-kernel>,\n\t<mailto:linux-arm-kernel-request@lists.infradead.org?subject=subscribe>","Cc":"devicetree@vger.kernel.org, Sean Wang <sean.wang@mediatek.com>,\n\tlinux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org,\n\tlinux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org","Content-Type":"text/plain; charset=\"us-ascii\"","Content-Transfer-Encoding":"7bit","Sender":"\"linux-arm-kernel\" <linux-arm-kernel-bounces@lists.infradead.org>","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"},"content":"From: Sean Wang <sean.wang@mediatek.com>\n\nAdd clock driver required by each function driver on MT7622 SoC with\nadding all clocks exported from every hardware subsystem such as topckgen,\napmixedsys, infracfg, pericfg , pciessys, ssusbsys, ethsys and audsys.\n\nChen Zhong (2):\n  clk: mediatek: add the option for determining PLL source clock\n  clk: mediatek: add clocks dt-bindings required header for MT7622 SoC\n\nSean Wang (2):\n  dt-bindings: clock: mediatek: document clk bindings for MediaTek\n    MT7622 SoC\n  clk: mediatek: add clock support for MT7622 SoC\n\n .../bindings/arm/mediatek/mediatek,apmixedsys.txt  |   1 +\n .../bindings/arm/mediatek/mediatek,audsys.txt      |  22 +\n .../bindings/arm/mediatek/mediatek,ethsys.txt      |   1 +\n .../bindings/arm/mediatek/mediatek,hifsys.txt      |   1 +\n .../bindings/arm/mediatek/mediatek,infracfg.txt    |   1 +\n .../bindings/arm/mediatek/mediatek,pciesys.txt     |  22 +\n .../bindings/arm/mediatek/mediatek,pericfg.txt     |   1 +\n .../bindings/arm/mediatek/mediatek,sgmiisys.txt    |  22 +\n .../bindings/arm/mediatek/mediatek,ssusbsys.txt    |  22 +\n .../bindings/arm/mediatek/mediatek,topckgen.txt    |   1 +\n drivers/clk/mediatek/Kconfig                       |  30 +\n drivers/clk/mediatek/Makefile                      |   4 +\n drivers/clk/mediatek/clk-mt7622-aud.c              | 195 ++++++\n drivers/clk/mediatek/clk-mt7622-eth.c              | 156 +++++\n drivers/clk/mediatek/clk-mt7622-hif.c              | 169 +++++\n drivers/clk/mediatek/clk-mt7622.c                  | 780 +++++++++++++++++++++\n drivers/clk/mediatek/clk-mtk.h                     |   1 +\n drivers/clk/mediatek/clk-pll.c                     |   5 +-\n include/dt-bindings/clock/mt7622-clk.h             | 289 ++++++++\n 19 files changed, 1722 insertions(+), 1 deletion(-)\n create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.txt\n create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,pciesys.txt\n create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,sgmiisys.txt\n create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,ssusbsys.txt\n create mode 100644 drivers/clk/mediatek/clk-mt7622-aud.c\n create mode 100644 drivers/clk/mediatek/clk-mt7622-eth.c\n create mode 100644 drivers/clk/mediatek/clk-mt7622-hif.c\n create mode 100644 drivers/clk/mediatek/clk-mt7622.c\n create mode 100644 include/dt-bindings/clock/mt7622-clk.h"}