{"id":816053,"url":"http://patchwork.ozlabs.org/api/covers/816053/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-pci/cover/1505889764-19397-1-git-send-email-mmaddireddy@nvidia.com/","project":{"id":28,"url":"http://patchwork.ozlabs.org/api/projects/28/?format=json","name":"Linux PCI development","link_name":"linux-pci","list_id":"linux-pci.vger.kernel.org","list_email":"linux-pci@vger.kernel.org","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<1505889764-19397-1-git-send-email-mmaddireddy@nvidia.com>","list_archive_url":null,"date":"2017-09-20T06:42:40","name":"[0/4] Add Tegra186 PCIe support","submitter":{"id":72399,"url":"http://patchwork.ozlabs.org/api/people/72399/?format=json","name":"Manikanta Maddireddy","email":"mmaddireddy@nvidia.com"},"mbox":"http://patchwork.ozlabs.org/project/linux-pci/cover/1505889764-19397-1-git-send-email-mmaddireddy@nvidia.com/mbox/","series":[{"id":4034,"url":"http://patchwork.ozlabs.org/api/series/4034/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-pci/list/?series=4034","date":"2017-09-20T06:42:41","name":"Add Tegra186 PCIe support","version":1,"mbox":"http://patchwork.ozlabs.org/series/4034/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/covers/816053/comments/","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=linux-pci-owner@vger.kernel.org;\n\treceiver=)","Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xxqxK0Jm2z9sP1\n\tfor ;\n\tWed, 20 Sep 2017 16:45:09 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751663AbdITGpH (ORCPT );\n\tWed, 20 Sep 2017 02:45:07 -0400","from hqemgate14.nvidia.com ([216.228.121.143]:1817 \"EHLO\n\thqemgate14.nvidia.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1751646AbdITGpH (ORCPT\n\t); Wed, 20 Sep 2017 02:45:07 -0400","from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by\n\thqemgate14.nvidia.com\n\tid ; Tue, 19 Sep 2017 23:44:36 -0700","from HQMAIL106.nvidia.com ([172.20.161.6])\n\tby hqpgpgate102.nvidia.com (PGP Universal service);\n\tTue, 19 Sep 2017 23:44:38 -0700","from HQMAIL112.nvidia.com (172.18.146.18) by HQMAIL106.nvidia.com\n\t(172.18.146.12) with Microsoft SMTP Server (TLS) id 15.0.1293.2;\n\tWed, 20 Sep 2017 06:43:06 +0000","from HQMAIL103.nvidia.com (172.20.187.11) by HQMAIL112.nvidia.com\n\t(172.18.146.18) with Microsoft SMTP Server (TLS) id 15.0.1293.2;\n\tWed, 20 Sep 2017 06:43:06 +0000","from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL103.nvidia.com\n\t(172.20.187.11) with Microsoft SMTP Server id 15.0.1293.2 via\n\tFrontend Transport; Wed, 20 Sep 2017 06:43:06 +0000","from manikanta-pc.nvidia.com (Not Verified[10.19.65.28]) by\n\thqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 5, 8150)\n\tid ; Tue, 19 Sep 2017 23:43:05 -0700"],"X-PGP-Universal":"processed;\n\tby hqpgpgate102.nvidia.com on Tue, 19 Sep 2017 23:44:38 -0700","From":"Manikanta Maddireddy ","To":", , ","CC":", ,\n\t\"Manikanta Maddireddy\" ","Subject":"[PATCH 0/4] Add Tegra186 PCIe support","Date":"Wed, 20 Sep 2017 12:12:40 +0530","Message-ID":"<1505889764-19397-1-git-send-email-mmaddireddy@nvidia.com>","X-Mailer":"git-send-email 2.1.4","X-NVConfidentiality":"public","MIME-Version":"1.0","Content-Type":"text/plain","Sender":"linux-pci-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"linux-pci@vger.kernel.org"},"content":"Tegra186 has three PCIe controllers which can be operated\nin 401, 211 or 111 lane configurations. Tegra TX2 platform\nhas x4 and M.2 Key E PCIe slots, these patches enables\nx4 slot. BPMP programs UPHY lane0 ownership to USB,\nso M.2 Key E PCIe will not work.\n\nTesting: x4 slot is verified with PCIe based USB3.1 card.\nPCIe link up, usb flash drive mounting and file copy are\nverified. Pasting PCIe link up logs below.\n\n[ 1.452512] tegra-pcie 10003000.pcie: 4x1, 1x1 configuration\n[ 1.452723] tegra-pcie 10003000.pcie: Failed to get supply 'dvdd-pex': -517\n[ 1.561824] ehci-pci: EHCI PCI platform driver\n[ 1.591587] ohci-pci: OHCI PCI platform driver\n[ 3.072464] tegra-pcie 10003000.pcie: 4x1, 1x1 configuration\n[ 3.078989] tegra-pcie 10003000.pcie: probing port 0, using 4 lanes\n[ 3.087272] tegra-pcie 10003000.pcie: Slot present pin change, signature: 00000018\n[ 3.128818] tegra-pcie 10003000.pcie: PCI host bridge to bus 0000:00\n[ 3.135174] pci_bus 0000:00: root bus resource [io 0x0000-0xffff]\n[ 3.141352] pci_bus 0000:00: root bus resource [mem 0x50100000-0x57ffffff]\n[ 3.148221] pci_bus 0000:00: root bus resource [mem 0x58000000-0x7fffffff pref]\n[ 3.155542] pci_bus 0000:00: root bus resource [bus 00-ff]\n[ 3.161173] pci 0000:00:01.0: [10de:10e5] type 01 class 0x060400\n[ 3.161188] pci_bus 0000:00: 2-byte config write to 0000:00:01.0 offset 0x4 may corrupt adjacent RW1C bits\n[ 3.170838] pci_bus 0000:00: 2-byte config write to 0000:00:01.0 offset 0x4 may corrupt adjacent RW1C bits\n[ 3.180532] pci_bus 0000:00: 2-byte config write to 0000:00:01.0 offset 0x52 may corrupt adjacent RW1C bits\n[ 3.190305] pci 0000:00:01.0: PME# supported from D0 D1 D2 D3hot D3cold\n[ 3.190312] pci_bus 0000:00: 2-byte config write to 0000:00:01.0 offset 0x4c may corrupt adjacent RW1C bits\n[ 3.200158] pci 0000:00:01.0: bridge configuration invalid ([bus 00-00]), reconfiguring\n[ 3.208158] pci_bus 0000:00: 2-byte config write to 0000:00:01.0 offset 0x3e may corrupt adjacent RW1C bits\n[ 3.217918] pci_bus 0000:00: 2-byte config write to 0000:00:01.0 offset 0x3e may corrupt adjacent RW1C bits\n[ 3.227649] pci_bus 0000:00: 2-byte config write to 0000:00:01.0 offset 0x3e may corrupt adjacent RW1C bits\n[ 3.237382] pci_bus 0000:00: 2-byte config write to 0000:00:01.0 offset 0x6 may corrupt adjacent RW1C bits\n[ 3.247135] pci 0000:01:00.0: [1b21:1242] type 00 class 0x0c0330\n[ 3.247157] pci_bus 0000:01: 2-byte config write to 0000:01:00.0 offset 0x4 may corrupt adjacent RW1C bits\n[ 3.256807] pci_bus 0000:01: 2-byte config write to 0000:01:00.0 offset 0x4 may corrupt adjacent RW1C bits\n[ 3.266477] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x00007fff 64bit]\n[ 3.266544] pci 0000:01:00.0: enabling Extended Tags\n[ 3.271622] pci 0000:01:00.0: PME# supported from D3hot D3cold\n[ 3.271775] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01\n[ 3.271798] pci 0000:00:01.0: BAR 14: assigned [mem 0x50100000-0x501fffff]\n[ 3.278671] pci 0000:01:00.0: BAR 0: assigned [mem 0x50100000-0x50107fff 64bit]\n[ 3.285993] pci 0000:00:01.0: PCI bridge to [bus 01]\n[ 3.290959] pci 0000:00:01.0: bridge window [mem 0x50100000-0x501fffff]\n[ 3.297763] pci 0000:00:01.0: nv_msi_ht_cap_quirk didn't locate host bridge\n[ 3.304784] pcieport 0000:00:01.0: enabling device (0000 -> 0002)\n[ 3.311014] pcieport 0000:00:01.0: Signaling PME with IRQ 57\n[ 3.316768] pci 0000:01:00.0: enabling device (0000 -> 0002)\n\nManikanta Maddireddy (4):\n dt-bindings: pci: tegra: Document Tegra186 PCIe DT\n PCI: tegra: Add Tegra186 PCIe support\n arm64: tegra: Add PCIe node for Tegra186\n arm64: tegra: Enable PCIe on Jetson TX2\n\n .../bindings/pci/nvidia,tegra20-pcie.txt | 134 ++++++++++++++++++++-\n arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi | 24 ++++\n arch/arm64/boot/dts/nvidia/tegra186.dtsi | 82 +++++++++++++\n drivers/pci/host/pci-tegra.c | 123 +++++++++++++++----\n 4 files changed, 338 insertions(+), 25 deletions(-)"}