{"id":815390,"url":"http://patchwork.ozlabs.org/api/covers/815390/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-pci/cover/20170919092658.22482-1-Zhiqiang.Hou@nxp.com/","project":{"id":28,"url":"http://patchwork.ozlabs.org/api/projects/28/?format=json","name":"Linux PCI development","link_name":"linux-pci","list_id":"linux-pci.vger.kernel.org","list_email":"linux-pci@vger.kernel.org","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20170919092658.22482-1-Zhiqiang.Hou@nxp.com>","list_archive_url":null,"date":"2017-09-19T09:26:53","name":"[0/5] arm64: add ls1012a and ls1046a pcie support","submitter":{"id":67929,"url":"http://patchwork.ozlabs.org/api/people/67929/?format=json","name":"Z.Q. Hou","email":"zhiqiang.hou@nxp.com"},"mbox":"http://patchwork.ozlabs.org/project/linux-pci/cover/20170919092658.22482-1-Zhiqiang.Hou@nxp.com/mbox/","series":[{"id":3816,"url":"http://patchwork.ozlabs.org/api/series/3816/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-pci/list/?series=3816","date":"2017-09-19T09:26:58","name":"arm64: add ls1012a and ls1046a pcie support","version":1,"mbox":"http://patchwork.ozlabs.org/series/3816/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/covers/815390/comments/","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=linux-pci-owner@vger.kernel.org;\n\treceiver=)","spf=fail (sender IP is 192.88.168.50)\n\tsmtp.mailfrom=nxp.com; nxp.com; dkim=none (message not signed)\n\theader.d=none;nxp.com; dmarc=fail action=none header.from=nxp.com;"],"Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xxJ1J6RYxz9s7B\n\tfor ;\n\tTue, 19 Sep 2017 19:46:44 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751445AbdISJo1 (ORCPT );\n\tTue, 19 Sep 2017 05:44:27 -0400","from mail-sn1nam01on0065.outbound.protection.outlook.com\n\t([104.47.32.65]:20512\n\t\"EHLO NAM01-SN1-obe.outbound.protection.outlook.com\"\n\trhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP\n\tid S1750972AbdISJoZ (ORCPT );\n\tTue, 19 Sep 2017 05:44:25 -0400","from BLUPR0301CA0019.namprd03.prod.outlook.com\n\t(2a01:111:e400:5259::29) by SN2PR03MB2365.namprd03.prod.outlook.com\n\t(2603:10b6:804:e::16) with Microsoft SMTP Server (version=TLS1_2,\n\tcipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id 15.20.56.11;\n\tTue, 19 Sep 2017 09:44:24 +0000","from BN1AFFO11OLC002.protection.gbl (2a01:111:f400:7c10::196) by\n\tBLUPR0301CA0019.outlook.office365.com (2a01:111:e400:5259::29) with\n\tMicrosoft SMTP Server (version=TLS1_2,\n\tcipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id 15.20.56.9 via\n\tFrontend Transport; Tue, 19 Sep 2017 09:44:24 +0000","from tx30smr01.am.freescale.net (192.88.168.50) by\n\tBN1AFFO11OLC002.mail.protection.outlook.com (10.58.53.73) with\n\tMicrosoft SMTP Server (version=TLS1_0,\n\tcipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.20.35.14\n\tvia Frontend Transport; Tue, 19 Sep 2017 09:44:23 +0000","from titan.ap.freescale.net ([10.192.208.233])\n\tby tx30smr01.am.freescale.net (8.14.3/8.14.0) with ESMTP id\n\tv8J9iINN014190; Tue, 19 Sep 2017 02:44:19 -0700"],"Received-SPF":"Fail (protection.outlook.com: domain of nxp.com does not\n\tdesignate 192.88.168.50 as permitted sender)\n\treceiver=protection.outlook.com; \n\tclient-ip=192.88.168.50; helo=tx30smr01.am.freescale.net;","From":"Zhiqiang Hou ","To":", ,\n\t, ,\n\t, ,\n\t, ,\n\t, , ,\n\t, ","CC":"Hou Zhiqiang ","Subject":"[PATCH 0/5] arm64: add ls1012a and ls1046a pcie support","Date":"Tue, 19 Sep 2017 17:26:53 +0800","Message-ID":"<20170919092658.22482-1-Zhiqiang.Hou@nxp.com>","X-Mailer":"git-send-email 2.14.1","X-EOPAttributedMessage":"0","X-Matching-Connectors":"131502878641310441;\n\t(91ab9b29-cfa4-454e-5278-08d120cd25b8); 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","X-Forefront-PRVS":"04359FAD81","SpamDiagnosticOutput":"1:99","SpamDiagnosticMetadata":"NSPM","X-MS-Exchange-CrossTenant-OriginalArrivalTime":"19 Sep 2017 09:44:23.9438\n\t(UTC)","X-MS-Exchange-CrossTenant-Id":"5afe0b00-7697-4969-b663-5eab37d5f47e","X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp":"TenantId=5afe0b00-7697-4969-b663-5eab37d5f47e;\n\tIp=[192.88.168.50]; Helo=[tx30smr01.am.freescale.net]","X-MS-Exchange-CrossTenant-FromEntityHeader":"HybridOnPrem","X-MS-Exchange-Transport-CrossTenantHeadersStamped":"SN2PR03MB2365","Sender":"linux-pci-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"linux-pci@vger.kernel.org"},"content":"From: Hou Zhiqiang \n\nThis patch set adds ls1012a MSI and PCIe support, including driver\nand device tree nodes. The ls1046a's MSI support patch and PCIe\ndriver patch has been applied, so only adds the PCIe device tree\nnodes.\n\nHou Zhiqiang (5):\n irqchip/ls-scfg-msi: add LS1012a MSI support\n arm64: dts: ls1012a: Add MSI controller DT node\n PCI: layerscape: Add support for ls1012a\n arm64: dts: ls1012a: Add PCIe controller DT node\n arm64: dts: ls1046a: add PCIe controller DT nodes\n\n .../interrupt-controller/fsl,ls-scfg-msi.txt | 1 +\n .../devicetree/bindings/pci/layerscape-pci.txt | 1 +\n arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi | 31 +++++++++\n arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 75 ++++++++++++++++++++++\n drivers/irqchip/irq-ls-scfg-msi.c | 1 +\n drivers/pci/dwc/pci-layerscape.c | 1 +\n 6 files changed, 110 insertions(+)"}