{"id":814709,"url":"http://patchwork.ozlabs.org/api/covers/814709/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/cover/20170917232010.14183-1-f4bug@amsat.org/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20170917232010.14183-1-f4bug@amsat.org>","list_archive_url":null,"date":"2017-09-17T23:20:04","name":"[v3,0/6] QOMify MIPS cpu","submitter":{"id":70924,"url":"http://patchwork.ozlabs.org/api/people/70924/?format=json","name":"Philippe Mathieu-Daudé","email":"f4bug@amsat.org"},"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/cover/20170917232010.14183-1-f4bug@amsat.org/mbox/","series":[{"id":3548,"url":"http://patchwork.ozlabs.org/api/series/3548/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=3548","date":"2017-09-17T23:20:04","name":"QOMify MIPS cpu","version":3,"mbox":"http://patchwork.ozlabs.org/series/3548/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/covers/814709/comments/","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; 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a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:sender:from:to:cc:subject:date:message-id\n\t:mime-version:content-transfer-encoding;\n\tbh=YVLQGR47yYijhywM+4oRaVC6Alah27U4/GURJaUVCoI=;\n\tb=pTXSf2DIMdWVGzwnipxqf+TewBYO/UqnsRoQxmKRGHDwPZsodh9G2jz1RaxLjQm5qT\n\tVwnPG5ZwbjZU30nO0GmF72lA+obFSfHkaBW9ZMM+A2xETCNWm40iaNBEiM/c51ikPfKQ\n\t0A1GKDCZySWTiWCdHKzqBxwopuXb4jO7RvEYnchdVMQqkWIQOOGq/kEsSNJfeyws8f4R\n\tFQYCwcXdAh5F9qcwx/6mLdbgttMbK79ugXN2pcQpN2u4Wf0YCMt90P3tQRBQFMCBL+rQ\n\t2OVQUg4eIicQYl5NDzZzhXlHteneefF6rJPcI3cXu/k0rIqlM9moxnkCml4ZI9kmzrLz\n\totAg==","X-Gm-Message-State":"AHPjjUhghT5Z8v7S0bRAEKEc3J+9tOaHKKQIajI/ezoIyXfwzNpurOS/\n\thQkne3kHGkXOkg==","X-Google-Smtp-Source":"AOwi7QCDdRIMovbNbroBhzwKLDcrpew81ahOUvwItR0ec7DWvfay6q0/8+6nUl3L8OkscVgrYC59Zg==","X-Received":"by 10.200.41.148 with SMTP id 20mr25360825qts.69.1505690426580; \n\tSun, 17 Sep 2017 16:20:26 -0700 (PDT)","From":"=?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= ","To":"Igor Mammedov ,\n\tEduardo Habkost , \n\tAurelien Jarno ,\n\tYongbok Kim ,\n\tMarcel Apfelbaum ","Date":"Sun, 17 Sep 2017 20:20:04 -0300","Message-Id":"<20170917232010.14183-1-f4bug@amsat.org>","X-Mailer":"git-send-email 2.14.1","MIME-Version":"1.0","Content-Type":"text/plain; charset=UTF-8","Content-Transfer-Encoding":"8bit","X-detected-operating-system":"by eggs.gnu.org: Genre and OS details not\n\trecognized.","X-Received-From":"2607:f8b0:400d:c0d::242","Subject":"[Qemu-devel] [PATCH v3 0/6] QOMify MIPS cpu","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"Thomas Huth , James Hogan ,\n\t=?utf-8?q?Herv=C3=A9_Poussineau?= ,\n\t=?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= ,\n\tqemu-devel@nongnu.org","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"\"Qemu-devel\"\n\t"},"content":"Hi,\n\nThis series is based on Igor's \"complete cpu QOMification\" [1] but only modify\nthe MIPS part. Igor posted an updated series [2].\n\nYongbok: this series is now ready to apply to your MIPS tree :)\n\nRegards,\n\nPhil.\n\n[1]: http://lists.nongnu.org/archive/html/qemu-devel/2017-07/msg04414.html\n[2]: http://lists.nongnu.org/archive/html/qemu-devel/2017-08/msg03364.html\n\nv3:\n- added Eduardo Habkost Acked-by and Reviewed-by\n- put Eduardo patch 4 review comment in commit message\n- address Eduardo's patch 5 review (use correct type, unnecessary null check)\n- drop patch 7 in favor of a \"generic mechanism to list CPU models using the\n QOM hierarchy\"\n\nv2: \n- added Igor and James Tested-by\n- squashed \"!fixup mips: now than MIPSCPU is QOMified, mark it abstract\"\n\nPS: code movement somehow triggers a \"binary vs unary operators\" confusion\n in checkpatch: \"ERROR: space prohibited after that '&' (ctx:WxW)\"\n\nIgor Mammedov (2):\n mips: MIPSCPU model subclasses\n mips: replace cpu_mips_init() with cpu_generic_init()\n\nPhilippe Mathieu-Daudé (4):\n mips: move hw/mips/cputimer.c to target/mips/\n mips: introduce internal.h and cleanup cpu.h\n mips: split cpu_mips_realize_env() out of cpu_mips_init()\n mips: call cpu_mips_realize_env() from mips_cpu_realizefn()\n\n target/mips/cpu-qom.h | 1 +\n target/mips/cpu.h | 357 +---------------------\n target/mips/internal.h | 422 ++++++++++++++++++++++++++\n hw/mips/cps.c | 2 +-\n hw/mips/mips_fulong2e.c | 2 +-\n hw/mips/mips_jazz.c | 2 +-\n hw/mips/mips_malta.c | 2 +-\n hw/mips/mips_mipssim.c | 2 +-\n hw/mips/mips_r4k.c | 2 +-\n hw/mips/cputimer.c => target/mips/cp0_timer.c | 2 +-\n target/mips/cpu.c | 54 +++-\n target/mips/gdbstub.c | 1 +\n target/mips/helper.c | 1 +\n target/mips/kvm.c | 1 +\n target/mips/machine.c | 1 +\n target/mips/msa_helper.c | 1 +\n target/mips/op_helper.c | 1 +\n target/mips/translate.c | 23 +-\n target/mips/translate_init.c | 58 +---\n hw/mips/Makefile.objs | 2 +-\n target/mips/Makefile.objs | 2 +-\n 21 files changed, 500 insertions(+), 439 deletions(-)\n create mode 100644 target/mips/internal.h\n rename hw/mips/cputimer.c => target/mips/cp0_timer.c (99%)"}